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检索条件"机构=National Key Laboratory for Parallel and Distributed Processing"

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Heterogeneity-Aware Peak Power Management for Accelerator-Based Systems

Heterogeneity-Aware Peak Power Management for Accelerator-Ba...

引用

International Conference on parallel and distributed Systems (ICPADS)

作者： Guibin Wang Yisong Lin National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

Power management has become one of the first-order considerations in high performance computing field. Many recent studies focus on optimizing the performance of a computer system within a given power budget. However, most existing solutions adopt fixed period control mechanism and are transparent to the running applications. Although the application-transparent control mechanism has relatively good portability, it exhibits low efficiency in accelerator-based heterogeneous parallel systems. In typical accelerator-based parallel systems, different processing units have largely different processing speeds and power consumption. Under a given power constraint, how to choose the processor to be slowed down and how to schedule a parallel task onto different processors for the maximum performance are different from those in homogeneous systems and have not been well studied. From the motivating example in this paper, we could find that in order to efficiently harness the heterogeneous parallel processing, one should not only perform dynamic voltage/frequency scaling (DVFS) to meet the power budget, but also tune the parallel task scheduling to adapt to the changes. In this paper, we propose a heterogeneity-aware peak power management, which extends existing application-transparent power controller with an application-aware power controller. Firstly, we theoretically analyze the conditions for the maximum performance given a power budget for heterogeneous systems. Based on this result, we provide a power-constrained parallel task partition algorithm, which coordinates parallel task partition and voltage scaling for heterogeneous processing units to achieve the optimal performance given a system power budget. Finally, we evaluate the proposed method on a typical CPU-GPU heterogeneous system, and validate the superiority of application-aware power controller over the existing method.

关键词： Graphics processing unit Power demand Partitioning algorithms Schedules Kernel Monitoring Benchmark testing

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parallelization of the Training for Face Detection with Transactional Memory

Parallelization of the Training for Face Detection with Tran...

引用

The International Conference on Automation and Robotics(ICAR 2011)

作者： Kun Zeng Key Laboratory and technology for National Defence of Parallel and Distributed Processing School of Computer National Univiersity of Defense Technology

The development of multi-core processor makes the parallelization of traditional sequential algorithms increasingly important. Meanwhile, transactional memory serves a good parallel programming model. This paper takes the advantage of software transactional memory to parallelize the Multi-Exit Asymmetric Adaboost algorithm for face detection. The parallel version is evaluated on three different implementations of software transactional memory. The experiment results show that the transactional memory based parallelization outperforms the traditional lock based approach. A speedup of nearly seven is achieved on a eight-core machine on an eight-core system.

关键词： Transactional Memory Face Detection Machine Learning Optimistic Algorithm Pessimistic Algorithm

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BIIP:Application Behavior-Aware Insertion Policies for Managing Shared Cache in CMPs

BIIP:Application Behavior-Aware Insertion Policies for Manag...

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2011 International Conference on Computers, Communications, Control and Automation

作者： Xiaomin Jia Ping Huang Tianlei Zhao Shubo Qi Guitao Fu Minxuan Zhang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology

Conventional replacement policy LRU(Least Recently Used) can significantly degrade the overall performance of shared cache of Chip Multi-Processors(CMPs), when the aggregate working set of multiple co-scheduled applications can not fit in cache. Different applications have different inherent cache access behavior characteristics. Replacement policy should take into account that fact so as to derive more performance benefit. This paper proposes application cache Behavior Identification based Insertion Policy(BIIP)replacement policies for managing shared cache in CMPs. BIIP seeks to make use of the cache access behavior characteristics of each co-scheduled application to smartly choose replacement policy. Our evaluation using a full system CMP simulator shows that BIIP improves the overall throughput by 14.8%,11.2%, 5.6% and 7.2% on average over baseline LRU policy,the prevailing cache partitioning scheme UCP and two other shared cache replacement policies PIPP, TADIP, respectively on a 4-core CMP with 16 SPEC CPU2006 workloads. Moreover,BIIP requires a total storage overhead of no more than several counters per core, and does not require changes to the current cache structure.

关键词： chip multi-processors(CMPs),application cache behaviors,last-level caches(LLC),insertion,replacement

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LoGPX: A new communication model for message-passing programs

LoGPX: A new communication model for message-passing program...

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International Symposium on Performance Evaluation of Computer & Telecommunication Systems SPECTS

作者： Yufei Lin Yuhua Tang Xiaowei Guo Xinhai Xu National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

Message Passing Interface (MPI) is a de facto standard for writing high-performance message-passing applications on distributed memory systems. To design effective applications and predict the performance of future systems, an accurate communication model is needed. In this paper, we discuss the characteristics of current systems and MPI implementations, then propose a more complete communication model, named LoGPX, which synthetically captures the influences of MPI communication protocol, the invoking time of communication primitive, hardware resource and network contention. Based on the model, we obtain the condition that the message transmission cost reaches the infimum, and we show that if ignoring some factors of LoGPX model, it can be degenerated to several popular models such as LogP, LogGP, LoGPC and LogGPO.

关键词： Protocols Receivers Message passing Network interfaces Hardware Analytical models Routing

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Filtering error log as time series in complex service-based storage systems

Filtering error log as time series in complex service-based ...

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International Conference on Networked Computing and Advanced Information Management (NCM)

作者： Xiang Rao Gang Yin Huaimin Wang Dianxi Shi Yanxu Zhu National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

Mining log pattern to analyze the faults in large scale distributed system is affected by the existence of redundant and ambiguous noisy error logs. While existing works try to compress logs in a coarse granularity from temporal and spatial view to remove the redundancy, they fail to reserve those ambiguous logs that might truly relate to a fault, which misleads the fault characterizing result. By modeling error logs as time series and examining the similarity between trash error log template and target error log, the ambiguous error logs are kept and the affected patterns can be effectively removed. Experiments in a practical complex service-based storage show that up to 92% of the affected patterns can be filtered.

关键词： Time series analysis Approximation methods Computer crashes Libraries Matched filters Transforms

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Fault Recovery Based on parallel Recomputing in Transactional Memory System

Fault Recovery Based on Parallel Recomputing in Transactiona...

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The 2011 International Conference on Electric and Electronics(EEIC 2011)

作者： Wei Song Jia Jia National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology

This paper addresses the issue of fault recovery in transactional memory,and proposes a method of fault recovery based on parallel recomputing in transactional memory *** method utilizes the dataversioning mechanism of transactional memory system to avoid the extra cost of state saving,rolls back a single transaction to avoid wasting the computing time of the fault-free transactions,and adopts the parallel recomputing method to reduce the cost of fault *** paper applies this method to Open TM programs,and proposes the implementation method of parallel recomputing in Open *** last,this paper tests the performance of this method through a test *** experimental results show that,compared with the fault recovery method of rolling back a single transaction,the parallel recomputing method in transactional memory system can execute the fault recovery quickly and accurately and the method has a well scalability.

关键词： Fault tolerance parallel recomputing Fault Recovery Transactional memory

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Cache Miss Analysis for GPU Programs Based on Stack Distance Profile

Cache Miss Analysis for GPU Programs Based on Stack Distance...

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International Conference on distributed Computing Systems

作者： Tao Tang Xuejun Yang Yisong Lin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

Using the graphics processing unit (GPU) to accelerate the general purpose computation has attracted much attention from both the academia and industry due to GPU's powerful computing capacity. Thus optimization of GPU programs has become a popular research direction. In order to support the general purpose computing more efficiently, GPU has integrated the general data cache to replace the existing software-managed on-chip memory. Consequently, improving the usage of the data cache becomes of vital importance to improve the performance of the GPU programs. The foundation of cache locality optimizations is efficient analysis and prediction of the cache behavior. Unfortunately, existing cache miss analysis models are based on sequential programs and thus cannot be used to analyze the GPU programs directly. In this paper, based on the deep analysis of GPU's execution model, we propose, for the first time, a cache miss analysis model for the GPU programs. We divide the problem into two subproblems: stack distance profile analysis of single thread block and cache contention analysis of multiple thread blocks. The experimental results from nine typical application kernels in the scientific computing field illustrate that our method is efficient and can be used to guide the cache locality optimizations for the GPU programs.

关键词： Graphics processing unit Instruction sets Kernel Analytical models Computational modeling Silicon Optimization

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Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA

Special-purposed VLIW architecture for IEEE-754 quadruple pr...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Yuanwu Lei Yong Dou Li Shen Jie Zhou Song Guo National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China

This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. Then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). The proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. The performance is improved through the explicitly parallel technology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. The experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library.

关键词： Strontium Lead Random access memory System-on-a-chip Artificial intelligence

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Power Optimization for GPU Programs Based on Software Prefetching

Power Optimization for GPU Programs Based on Software Prefet...

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IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Yisong Lin Tao Tang Guibin Wang Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing National University of Defense and Technology Changsha China

GPUs render higher computing unit density than contemporary CPUs and thus exhibit much higher power consumption despite its higher power efficiency. The power consumption has become an important issue that impacts CPU's applications, thereby necessitating the low power optimization technology for GPUs. Software prefetching is an efficient way to alleviate the memory wall problem which overlaps the computing and memory access latencies. However, software prefetching will cause some power overhead because it increases the number and density of the instructions. Thus, we should consider the balance between the performance income and the power overhead when applying the optimization. To address this problem, in this paper we first analyze the multi-thread execution model of GPU and validate the potential space of software prefetching optimization. Then we give the software prefetching method for GPU programs to improve the performance. Aiming at two different objects: energy optimization under performance constraint and performance optimization under power constraint, we discuss the optimization methods based on software prefetching and dynamic voltage scaling technologies. The experimental results show that our method can efficiently optimize the energy consumption (performance) under the performance (power) constraint.

关键词： Prefetching Graphics processing unit Optimization Power demand Registers

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Approximating Quantified SMT-Solving with SAT

Approximating Quantified SMT-Solving with SAT

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International Conference on Secure Software Integration and Reliability Improvement Companion (SSIRI-C)

作者： Xianjin Fu Wanwei Liu Jing Li National Laboratory for Parallel & Distributed Processing National University of Defense Technology Changsha China

Satisfiability Modulo Theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers and combination of theorems is a long-standing challenge, which has been a major bottleneck of practical application of SMT solvers in some fields. We reveal a decidable fragment of FOL involving quantifiers, which could not be solved by SMT solvers such as Z3, CVC3, etc., and show how to convert them into model checking problems.

关键词： Connectors Semantics Labeling Benchmark testing Cognition Encoding Computational modeling

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