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Automatic concurrency management for distributed applications

Automatic concurrency management for distributed application...

引用

15th IEEE Symposium on Computers and Communications, ISCC 2010

作者： Li, Huiba Liu, Shengyun Peng, Yuxing Li, Dongsheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424477555

Building distributed applications is difficult mostly because of concurrency management. Existing approaches primarily include events and threads. Researchers and developers have been debating for decades to prove which is superior. Although the conclusion is far from obvious, this long debate clearly shows that neither of them is perfect. One of the problems is that they are both complex and error-prone. Both events and threads need the programmers to explicitly manage concurrency, and we believe it is just the source of difficulties. In this paper, we propose a novel approach-automatic concurrency management by the runtime system. It dynamically analyzes the programs to discover potential concurrency opportunities;and it dynamically schedules the communication and the computation tasks, resulting in automatic concurrent execution. This approach is inspired by the instruction scheduling technologies used in modern microprocessors, which dynamically exploits instruction-level parallelism. However, hardware scheduling algorithms do not fit software in many aspects, thus we have to design a new scheme completely from scratch. automatic concurrency management is a runtime technique with no modification to the language, compiler or byte code, so it is good at backward compatibility. It is essentially a dynamic optimization for networking programs. © 2010 IEEE.

关键词： Scheduling algorithms

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Design and practice on iVCE for memory system

Design and practice on iVCE for memory system

引用

16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Chu, Rui Tian, Tian Lin, Zhenli National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9780769543079

As one of the components in iVCE software platform, iVCE/M devotes to the performance improvement of the I/O-intensive and memory-intensive applications with efficient aggregation of distributed memory resources. To facilitate the deployment of iVCE/M, the data locating algorithm with balanced time and space cost, as well as the transparent interface for the legacy applications without code modification, are both significant in the implementation of iVCE/M. We propose the logarithmic search tree based client-side metadata structure to accelerate the data locating using moderate memory consumption, the implicit I/O redirection mechanism, and the implementation of iVCE/M based disk cache system. The experiments with cross domain emulation prove that the scheme is applicable to exploit the distributed memory resources for applications with small granularity I/O accesses. © 2010 IEEE.

关键词： Application programs

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HiAL-Ckpt: A hierarchical application-level checkpointing for CPU-GPU hybrid systems

HiAL-Ckpt: A hierarchical application-level checkpointing fo...

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International Conference on Computer Science and Education

作者： Xu, Xinhai Lin, Yufei Tang, Tao Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

In light of its powerful computing capacity and high energy efficiency, GPU (graphics processing unit) has become a focus in the research field of HPC (High Performance Computing). CPU-GPU heterogeneous parallel systems have become a new development trend of super-computer. However, the inherent unreliability of the GPU hardware deteriorates the reliability of super-computer. We have researched on the fault-tolerance(FT) technique for CPU-GPU heterogeneous parallel systems, and introduced a new checkpointing mechanism, i.e., the hierarchical application-level checkpointing, for such systems. The basic idea of this new checkpointing mechanism is checkpointing at two independent levels, i.e., CPU level and GPU level, to tolerate CPU and GPU faults respectively. Based on the idea, we have also designed and implemented a hierarchical application-level checkpointing tool "HiAL-Ckpt". Using this tool, programmers can insert two kinds of directives, i.e., CPU directives and GPU directives into a program, and the compiler will transform the directives into CPU or GPU checkpointing codes according to their nature. From the case study of SWIM, a test bench from spec2000 benchmark suite, we have demonstrated the validity of the hierarchical application-level checkpointing technique. The experimental results show that the falut-tolerance temporal cost of HiAL-Ckpt for SWIM is only 2.25%, compared with the executing time of SWIM without any FT work. ©2010 IEEE.

关键词： Graphics processing unit

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Mapping OpenMP concepts to the stream programming model

Mapping OpenMP concepts to the stream programming model

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International Conference on Computer Science and Education

作者： Tang, Tao Lin, Yisong Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

OpenMP is a widely used parallel programming model on traditional multi-core processors. Generally, OpenMP is used to develop fine-grained parallelism through a multithread model. Stream programming model is a new kind of parallel programming model for stream architectures. OpenMP bears a resemblance to the stream programming model at some level. The transformation between the two models has attracted much attention from the research community, since it is the foundation of porting programs between the two architectures. Most related researches focus on the efficiency of porting existing parallel programs to the new architectures such as GPUs. Very few of these studies, however, focus on the portative problem systematically, namely, what kind of parallel programs can be or should be transplanted into stream programs and mapped to run on the stream processors. In this paper, we study the mapping relationship of parallel mechanism in OpenMP to the stream programming model, and point out those parallel mechanisms in OpenMP that are infeasible or undesirable for stream programs. By analyzing two typical benchmarks, we draw the conclusion that a majority of scientific applications are suitable to be mapped to the stream programming model. Our conclusion effectively validates the idea of accelerating scientific applications with the stream processors. ©2010 IEEE.

关键词： Mapping

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Media access control protocol based on hybrid antennas in ad hoc networks

Media access control protocol based on hybrid antennas in ad...

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International Conference on Autonomic and Trusted Computing

作者： Ding, Yanrong Wang, Xiaodong Shen, Hu Guo, Pengyu National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769542720

Nested Circular Directional MAC, a modified medium access control protocol of DMAC protocol, is proposed in this paper to support both directional antennas and omni-directional antennas simultaneously in one Ad Hoc network. Omni-directional antennas follow the RTS/CTS mechanism which is multi-hop and directional antennas follow the DRTS/DCTS mechanism, ensuring the asymmetric communication effectively. In order to resolve new deafness problem and hidden terminal problem, the directional antennas also use circular DRTS and nested antenna circumrotation. Simulation results show that NCDMAC supports hybrid antennas effectively and is better than MMAC and Circular-MAC in terms of increasing throughput, but it also increases the communication delay. © 2010 IEEE.

关键词： Ad hoc networks

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An efficient load balancing method for constant degree P2P systems

An efficient load balancing method for constant degree P2P s...

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2010 International Conference on Computer Design and Applications, ICCDA 2010

作者： Wang, XiaoHai Peng, YuXing Li, DongSheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781424471638

Constant degree P2P systems are turning into the P2P domain's promising hotspot due to their good properties. However, it is often hard to convert a standard constant degree digraph to a flexible DHT schema adapting to dynamic P2P environments. Thus, most research about constant degree P2P focus on DHT's construction and maintenance, while leaving optimization and supporting to upper-layer application behind, such as complex query, load balance, etc. Combining constant degree topology's bit-shift routing schema, we presents an efficient load balancing algorithm based on Reverse Spanning Tree (REST) for constant degree P2P systems. Using the statistic information in joining process, REST judges how many Virtual Servers that a new join super peer can run, and then join all virtual servers evenly and fast with low cost based on the Spanning Tree Peer Set. Experimental results show, without additional data structure, REST keeps the constant degree P2P system load-balanced by assuring each peer of owning a key space proportional to its capability. © 2010 IEEE.

关键词： Trees (mathematics)

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Dynamic program Behavior Identification for high performance CMPs with private LLCs

Dynamic program Behavior Identification for high performance...

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作者： Jia, Xiaomin Lu, Pingjing Sun, Caixia Zhang, Minxuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology China

Chip Multi-Processors (CMPs) emerge as a mainstream architectural design alternative for high performance parallel and distributed computing. Last Level Cache (LLC) management is critical to CMPs because off-chip accesses often require a long latency. Due to its short access latency, well performance isolation and easy scalability, private cache is an attractive design alternative for LLC of CMPs. This paper proposes program Behavior Identification-based Cache Sharing (BICS) for LLC management. BICS is based on a private cache organization for the shorter access latency. Meanwhile, BICS tries to simulate a shared cache organization by allowing evicted blocks of one private LLC to be saved at peer LLCs. This technique is called spilling. BICS identifies cache behavior types of applications at runtime. When a cache block is evicted from a private LLC, cache behavior characteristics of the local application are evaluated so as to determine whether the block is to be spilled. Spilled blocks are allowed to replace some valid blocks of the peer LLCs as long as the interference is within a reasonable level. Experimental results using a full system CMP simulator show that BICS improves the overall throughput by as much as 14.5%, 12.6%, 11.0% and 11.7% (on average 8.8%, 4.8%, 4.0% and 6.8%) over private cache, shared cache, Utility-based Cache Partitioning (UCP) scheme and the baseline spilling-based organization Cooperative Caching (CC) respectively on a 4-core CMP for SPEC CPU2006 benchmarks. Copyright© 2010.

关键词： Integrated circuit design

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Nexus: Speculative execution for event-driven networking programs

Nexus: Speculative execution for event-driven networking pro...

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16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Li, Huiba Lu, Xicheng Peng, Yuxing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769543079

The efficiency of communication is a key factor to the performance of networking applications, and concurrent communication is an important approach to the efficiency of communication. However, many concurrency opportunities are very difficult to exploit because they depend on some undeterministic conditions. If these conditions are highly predictable, speculative execution can be a very effective approach to cope with the uncertainties. Existing researches on speculation seldom target at networking systems, and none of them can handle the event-driven model that is very popular in such systems. In this paper, we propose Nexus, a novel speculation scheme that supports event-driven networking applications. Nexus analyzes the dependence relationship of events, and performs speculation according to the duality of events and threads. Evaluation on a prototype implementation of nexus shows that this approach can significantly reduces the time needed to complete an event-driven program. © 2010 IEEE.

关键词： Efficiency

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Accelerating MatLab code using GPU: A review of tools and strategies

Accelerating MatLab code using GPU: A review of tools and st...

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International Conference on Artificial Intelligence, Management Science and Electronic Commerce (AIMSEC)

作者： Baida Zhang Shuai Xu Feng Zhang Yuan Bi Linqi Huang National laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China Department of Information Engineering Academy of Armored Forces Engineering Beijing China Inspur (Beijing) Electronic Information Industry Company Limited Beijing China Naval Academy of Armament Beijing China School of Resources and Safety Engineering Central South University Changsha China

Lots of toolboxes of accelerating MatLab using GPU are available now[1], but, users are confused by which toolbox is best suitable for a particular task. Three toolboxes-Jacket, GPUmat, and parallel Computing Toolbox of MatLab are selected. For each toolbox, its advantages and pitfalls are reviewed, with an aim to allow the reader to identify which toolbox is appropriate for a given task. Strategies of whether a function should execute on GPU are given after a formula analysis. The analysis is also a framework for program automatically decides which function is cost-efficient to execute on GPU. A series of benchmark of different types of computing, including data transfer between GPU and CPU, data matrix Generation, matrix operation and GPU functions were tested in all three toolboxes. And the results show that Jacket is the best one. Some advices to improve the performance of toolboxes are given in the end.

关键词： Graphics processing unit Acceleration parallel processing Computer architecture Conferences Licenses MATLAB

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Evaluating the performance and accuracy impact of trace generation to the bigsim emulator

Evaluating the performance and accuracy impact of trace gene...

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10th IEEE International Conference on Computer and Information Technology, CIT-2010, 7th IEEE International Conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Che, Yonggang Xu, Chuanfu Lu, Pingjing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769541082

This paper quantitatively studies the trace effects to the performance and accuracy of the BigSim Emulator, a scalable parallel emulator for large-scale computers. To assess the accuracy effect we modify the emulator code to collect the predicted computation time. Four MPI programs with different computation to communication ratios are used as benchmarks. The emulation time and the predicted computation time, both when trace generation are enabled and disabled, are collected on two parallel host machines. The results show that although the BigSim Emulator only traces communication events and dependencies, trace generation still evidently degrades the emulation performance for programs with high communication to computation ratios. Trace generation also significantly affects the accuracy of the predicted computation time for communication intensive programs, which is an issue that can not be overlooked. © 2010 IEEE.

关键词： BigSim emulator MPI programs digital simulation emulator code large scale computers message passing parallel host machines parallel programming performance evaluation scalable parallel emulator trace generation accuracy impact

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