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A Data Communication Scheduler for Stream Programs on CPU-GPU Platform

A Data Communication Scheduler for Stream Programs on CPU-GP...

引用

International Conference on Computer and Information Technology (CIT)

作者： Tao Tang Xinhai Xu Yisong Lin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

In recent years, heterogeneous parallel system have become a focus research area in high performance computing field. Generally, in a heterogeneous parallel system, CPU provides the basic computing environment and special purpose accelerator (GPU in this paper) provides high computing performance. However, the overall performance of the system is prone to be limited by the data communication between the CPU and the GPU. Data communication is typically used to synchronize the array on the CPU and the stream (in AMD's terminology) on the GPU. In many cases, programmers just add data synchronization for each GPU invoking independently. It is easy to program in this manner but much redundant communication may be introduced, which will dramatically degrade the overall performance. To alleviate this problem, based on the stream programming model, we propose a heuristic data communication schedule approach in this paper. By analyzing the state transition of stream/array data pair, relaxing the synchronization strategy conditionally and considering optimization for branch and loop control structure, our approach can significantly reduce the redundant data communication in most cases.

关键词： Graphics processing unit Data communication Arrays Kernel Streaming media Schedules

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The Composability Problem of Events and Threads in distributed Systems

The Composability Problem of Events and Threads in Distribut...

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2010 2nd International Conference on Education Technology and Computer(第二届IEEE教育技术与计算机国际会议 ICETC 2010)

作者： Huiba Li Yuxing Peng Xicheng Lu National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China 410073

ISBN: (纸本)9781424463671;9781424463688;9781424463701

Event-driven programming has been a relatively hot topic in distributed systems development. Having worked on these systems for years, we now believe that it is not the best choice. Besides the wellknown "stack ripping" problem, we argue that it greatly influences the composability of software modules. Preemptive threads are also short of composability because of data-races and locks. Lacking of composability can result in systems with little vitality. Cooperative threading (or coroutine), on the contrary, is almost free of this problem, so we advocate it as the primary concurrency model for most distributed systems.

关键词： distributed systems thread event composability

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A simulated annealing technique for optimizing timewarp simulation

A simulated annealing technique for optimizing timewarp simu...

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2010 International Conference on Computer Modeling and Simulation, ICCMS 2010

作者： Zhang, Wei Meraji, Sina Wang, Jun Tropper, Carl National Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha 410073 China School of Computer Science McGill University Montreal H3A 2A7 Canada

ISBN: (纸本)9780769539416

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of Time Warp simulations. © 2010 IEEE.

关键词： Simulated annealing

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Link Scheduling in Wireless Networks with Successive Interference Cancellation

Link Scheduling in Wireless Networks with Successive Interfe...

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International Conference on Mobile Ad-hoc and Sensor Networks, MSN

作者： Shaohe Lv Xiaodong Wang Xingming Zhou National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China

Successive interference cancellation (SIC) is an effective technique of multipacket reception to combat interference. As not all collision are resolvable, careful transmission coordination is required. We study link scheduling in wireless networks with SIC at the physical layer. A new model, simultaneity graph (SG), is proposed to characterize the link correlation introduced by SIC. Then two new scheduling schemes are presented: 1) a slot-oriented scheme which assigns a maximal feasible link set to a time slot and 2) a link-oriented scheme which assigns each link a sufficient number of slots. The performance is evaluated by simulations and the results demonstrate that the throughput gain is on average 50% and up to 110% over IEEE 802.11. The complexity of SG is only a bit higher than that of the available widely-used models (e.g., conflict graph).

关键词： Interference Optimal scheduling Silicon carbide Schedules Scheduling Receivers Measurement

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Scheduling under SINR Model in Ad Hoc Networks with Successive Interference Cancellation

Scheduling under SINR Model in Ad Hoc Networks with Successi...

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2010 IEEE Global Telecommunications Conference GLOBECOM 2010

作者： Shaohe Lv Xiaodong Wang Xingming Zhou National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China

Successive interference cancellation (SIC) is an effective way of multipacket reception to combat interference. We study link scheduling under SINR (Signal to Interference Noise Ratio) model in ad hoc networks with SIC at physical layer. The facts that interference is accumulated and the links decoded sequentially by SIC are correlated pose key technical challenges. We propose conflict set graph (CSG) to characterize the interference and define interference degree to measure the interference of a link. As scheduling over CSG is NP-hard, independent set based greedy scheme is explored to efficiently construct maximal feasible schedule. The performance is evaluated by simulations. As compared to the simple greedy method, the throughput gain is on average 30% and up to 60%.

关键词： Interference Silicon carbide Peer to peer computing Throughput Signal to noise ratio Wireless networks Transmitters

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Optimization and Implementation of LBM Benchmark on Multithreaded GPU

Optimization and Implementation of LBM Benchmark on Multithr...

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International Conference on Data Storage and Data Engineering (DSDE)

作者： Xiaoguang Ren Yuhua Tang Guibin Wang Tao Tang Xudong Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781424456789;9780769539584

With fast development of transistor technology, Graphic processing Unit(GPU) is increasingly used in the non-graphics applications, and major GPU hardware vendors have introduced software stacks for their own GPUs, such as Brook+ for AMD GPU. Compared with the traditional parallel systems, heterogeneous systems integerating stream-based multi-threaded GPUs provide higher parallel computing capabilities with lower cost. However, porting traditional applications to the heterogeneous systems makes new demand of application optimization on GPU. Based on the AMD's Brook+ platform, we explored application optimization features on AMD GPU by optimizing and implementing the benchmark LBM from SPEC2006. To improve the program locality, we optimized the original data layout of LBM. Using the short vector data types mechanism provided by Brook+, we also optimized the GPU's bandwidth utilization and its thread processors' efficiency. Through the branch elimination technique, we reduced the performance lose caused by branch divergences in the kernel, which is due to the GPU's SIMD executing mode. The experiment results show that data layout, memory bandwidth, branch paths and other factors have a close effect on the performance of program execution on the GPU. Through all the optimizations, we finally got a speedup of 22x (single-precision) and 19x (double-precision) over the original serial benchmark code on a Quad-core CPU, and a speedup of 4x (single-precision) and 8.7x (double-precision) over the original OMP benchmark code on a 8-core CPU.

关键词： Application software Graphics processing unit parallel processing Computer architecture Biomedical computing Computational fluid dynamics Computational modeling

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Evaluating the Performance and Accuracy Impact of Trace Generation to the BigSim Emulator

Evaluating the Performance and Accuracy Impact of Trace Gene...

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International Conference on Computer and Information Technology (CIT)

作者： Yonggang Che Chuanfu Xu Pingjing Lu National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

This paper quantitatively studies the trace effects to the performance and accuracy of the BigSim Emulator, a scalable parallel emulator for large-scale computers. To assess the accuracy effect we modify the emulator code to collect the predicted computation time. Four MPI programs with different computation to communication ratios are used as benchmarks. The emulation time and the predicted computation time, both when trace generation are enabled and disabled, are collected on two parallel host machines. The results show that although the BigSim Emulator only traces communication events and dependencies, trace generation still evidently degrades the emulation performance for programs with high communication to computation ratios. Trace generation also significantly affects the accuracy of the predicted computation time for communication intensive programs, which is an issue that can not be overlooked.

关键词： Emulation Accuracy Runtime Benchmark testing Program processors Predictive models Jacobian matrices

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Optimizing Adaptive Synchronization in parallel Simulators for Large-scale parallel Systems and Applications

Optimizing Adaptive Synchronization in Parallel Simulators f...

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International Conference on Computer and Information Technology (CIT)

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

This paper addresses the optimization of parallel simulators for large-scale parallel systems and applications. Such simulators are often based on parallel discrete event simulation with conservative or optimistic protocols to synchronize the simulating processes. The paper considers how available future information about events and application behaviors can be efficiently extracted and further exploited to improve the performance of adaptive optimistic protocols. First, we extract information about future events and their dependencies in application traces to guide adaptive adjustments of time window in trace-driven parallel simulation. Second, we use information about application behaviors, specifically the iterative behavior found in many applications, to avoid the unnecessary adjustments of time window. These techniques are implemented in the BigSim simulator and tested by real-world and standard benchmark applications including Jacobi3D and HPL. The results show that our optimization approaches can reduce the execution times of simulation ranging from 11% up to 32%. Moreover, our methods are easy to implement and don't need to augment compilers or even modify the core codes of parallel simulators.

关键词： Adaptation model Computational modeling Schedules Optimization Protocols Synchronization Analytical models

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Efficient Virtual Machine Deployment in Large Scale Resource Environment

Efficient Virtual Machine Deployment in Large Scale Resource...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Feng Huang Dongsheng Li National Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha China

Combining virtual machine technology, virtual computing is able to effectively aggregate the widely distributed resources to provide users services. We view the federation of multiple data centers and voluntary resources on the Internet as a very large scale resource pool. Based on the tree structure of the pool, this paper proposes a virtual machine deployment algorithm, called iVDA, considers users' requests and the capabilities of the physical resources as well as the dynamic load, implements an adaptive mechanism to scheduling servers to host virtual machines forming virtual execution environments for various applications, and supports on-demand computing.

关键词： Virtual machining Servers Heuristic algorithms Internet Dynamic scheduling Cloning Processor scheduling

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Towards Online Application Cache Behaviors Identification in CMPs

Towards Online Application Cache Behaviors Identification in...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Xiaomin Jia Jiang Jiang Tianlei Zhao Shubo Qi Minxuan Zhang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

On chip multiprocessors (CMPs) platforms, multiple co-scheduled applications can severely degrade performance and quality of service (QoS) when they contend for last-level cache (LLC) resources. Whether an application will impose destructive interference on co-scheduled applications is largely dependent on its own inherent cache access behavior characteristics. In this work, we first present case studies that show how inter-application interferences result in undesirable performance in both shared and private cache based LLC designs. We then propose a new online approach for application cache behavior identification on the basis of detailed simulation and analysis with SPEC CPU2006 benchmarks. We demonstrate that our approach can more concisely identify application cache behaviors. Moreover, the proposed approach can be implemented directly in hardware to dynamically identify the application cache behaviors at runtime. Finally, we show with two case studies that how the proposed approach can be adopted by both shared and private based cache sharing mechanisms, i.e. cache partitioning algorithms (CPAs) and cache spilling techniques, for more concise cache resource management.

关键词： Benchmark testing Measurement Throughput Servers Interference Aerospace electronics Heuristic algorithms

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