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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Guiming Wu Yong Dou Miao Wang National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China Jiangnan Institute of Computing Technology Wuxi China

We present a high performance and memory efficient hardware implementation of matrix multiplication for dense matrices of any size on the FPGA devices. By applying a series of transformations and optimizations on the original serial algorithm, we can obtain an I/O and memory optimized block algorithm for matrix multiplication on FPGAs. A linear array of processing elements (PEs) is proposed to implement this block algorithm. We show significant reduction in hardware resources consuming compared to the related work while increasing clock frequency. Moreover, the memory requirement can be reduced to O(S) from O(S 2 ), where S is the block size. Therefore, more PEs can be integrated into the same FPGA devices.

关键词： Field programmable gate arrays Arrays Random access memory Algorithm design and analysis Hardware Memory management Optimization

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Automatic synthesis of processor arrays with local memories on FPGAs

Automatic synthesis of processor arrays with local memories ...

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IEEE International Conference on Field-Programmable Technology (FPT)

In this paper, we present an automatic synthesis framework to map loop nests to processor arrays with local memories on FPGAs. An affine transformation approach is firstly proposed to address space-time mapping problem. Then a data-driven architecture model is introduced to enable automatic generation of processor arrays by extracting this data-driven architecture model from transformed loop nests. Some techniques including memory allocation, communication generation and control generation are presented. Synthesizable RTL codes can be easily generated from the architecture model built by these techniques. A preliminary synthesis tool is implemented based on PLUTO, an automatic polyhedral source-to-source transformation and parallelization framework.

关键词： parallel processing Registers Field programmable gate arrays Radiation detectors Arrays Computational modeling

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Proceedings - International Conference on Quality Software: Message from the Program Chairs

Proceedings - International Conference on Quality Software

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Proceedings - International Conference on Quality Software 2010年 xi页

作者： Wang, Ji Chan, Wing Kwong Kuo, Fei-Ching National Laboratory for Parallel and Distributed Processing Changsha China City University of Hong Kong Hong Kong Hong Kong Swinburne University of Technology Australia

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Versatile Stack Management for Multitasking Sensor Networks

Versatile Stack Management for Multitasking Sensor Networks

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IEEE International Conference on distributed Computing Systems

作者： Rui Chu Lin Gu Yunhao Liu Mo Li Xicheng Lu National Laboratory for Parallel and Distributed Processing National University of Defense Technology Department of Computer Science and Engineering Hong Kong University of Science and Technology

ISBN: (纸本)9781424472611;9780769540597

The networked application environment has motivated the development of multitasking operating systems for sensor networks and other low-power electronic devices, but their multitasking capability is severely limited because traditional stack management techniques perform poorly on small-memory systems. In this paper, we show that combining binary translation and a new kernel runtime can lead to efficient OS designs on resource-constrained platforms. We introduce SenSmart, a multitasking OS for sensor networks, and present new OS design techniques for supporting preemptive multi-task scheduling, memory isolation, and versatile stack management. We have implemented SenSmart on MICA2/MICAz motes. Evaluation shows that SenSmart performs efficient binary translation and demonstrates a significantly better capability in managing concurrent tasks than other sensornet operating systems.

关键词： parallel processing (COMPUTERS) Sensor networks Electron devices Furnace conveyors Cache Memory System Operating systems osmium

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Blocking LU Decomposition for FPGAs

Blocking LU Decomposition for FPGAs

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Guiming Wu Yong Dou Gregory D. Peterson National Laboratory for Parallel & Distributed Processing National University of Defense Technology Changsha China Electrical Engineering and Computer Science University of Tennessee Knoxville TN USA

To efficiently perform large matrix LU decomposition on FPGAs with limited local memory, the original algorithm needs to be blocked. In this paper, we propose a block LU decomposition algorithm for FPGAs, which is applicable for matrices of arbitrary size. We introduce a high performance hardware design, which mainly consists of a linear array of processing elements (PEs), to implement our block LU decomposition algorithm. A total of 36 PEs can be integrated into a Xilinx Virtex-5 xc5vlx330 FPGA on our self-designed PCI-Express card, reaching a sustained performance of 8.50 GFLOPS at 133 MHz, which outperforms previous work.

关键词： Field programmable gate arrays Matrix decomposition Hardware Power engineering computing Algorithm design and analysis Linear algebra Computer applications Concurrent computing distributed computing Laboratories

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Routing with uncertainty in wireless mesh networks

Routing with uncertainty in wireless mesh networks

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International Workshop on Quality of Service

作者： Fajun Chen Jiangchuan Liu Zongpeng Li Yijie Wang Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing National University of Defense Technology China School of Computing Science Simon Fraser University Department of Computer Science University of Caglary

Existing routing protocols for Wireless Mesh Networks (WMNs) are generally optimized with statistical link measures, while not addressing on the intrinsic uncertainty of wireless links. We show evidence that, with the transient link uncertainties at PHY and MAC layers, a pseudo-deterministic routing protocol that relies on average or historic statistics can hardly explore the full potentials of a multi-hop wireless mesh. We study optimal WMN routing using probing-based online anypath forwarding, with explicit consideration of transient link uncertainties. We show the underlying connection between WMN routing and the classic Canadian Traveller Problem (CTP). Inspired by a stochastic recoverable version of CTP (SRCTP), we develop a practical SRCTP-based online routing algorithm under link uncertainties. We study how dynamic next hop selection can be done with low cost, and derive a systematic selection order for minimizing transmission delay. We conduct simulation studies to verify the effectiveness of the SRCTP algorithms under diverse network configurations. In particular, compared to deterministic routing, reduction of end-to-end delay (51.15~73.02%) and improvement on packet delivery ratio (99.76%) are observed.

关键词： Uncertainty Wireless mesh networks Delay Routing protocols Physical layer Statistics Stochastic processes Relays Computer networks Concurrent computing

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Using Redundant Threads for Fault Tolerance of OpenMP Programs

Using Redundant Threads for Fault Tolerance of OpenMP Progra...

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International Conference on Information Science and Applications (ICISA)

作者： Hongyi Fu Yan Ding Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China Section #620 School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424459421

As the wide application of multi-core processor architecture in the domain of high performance computing, fault tolerance for shared memory parallel programs becomes a hot spot of research. For years, checkpointing has been the dominant fault tolerance technology in this field, and recently, many research works have been engaged with it. However, to those programs which deal with large amount of data, checkpointing may induce massive I/O transfer, which will adversely affect scalability. To deal with such a problem, this paper proposes a fault tolerance approach, making use of redundancy, for shared memory parallel programs. Our scheme avoids saving and restoring computational state during the program's execution, hence does not involve I/O operations, so presents explicit advantage over checkpointing in scalability. In this paper, we introduce our approach and the related compiler tool in detail, and give the experimental evaluation result.

关键词： Fault tolerance Checkpointing Scalability Hardware Application software Multicore processing High performance computing Laboratories distributed processing

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A Simulated Annealing Technique for Optimizing Time Warp Simulation

A Simulated Annealing Technique for Optimizing Time Warp Sim...

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International Conference on Computer Modeling and Simulation, ICCMS

作者： Wei Zhang Sina Meraji Jun Wang Carl Tropper National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha China School of Computer Science McGill University Montreal Canada

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of time warp simulations.

关键词： Time warp simulation Simulated annealing Circuit simulation Computational modeling Hardware design languages Discrete event simulation Computer simulation Voltage control Concurrent computing Computer science

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Effect of quantum capacitance on switching speed in T-CNFETs

Effect of quantum capacitance on switching speed in T-CNFETs

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IEEE International Nanoelectronics Conference (INEC)

作者： Hailiang Zhou Minxuan Zhang Yue Hao National Laboratory of Parallel and Distributed processing School of Computer National University of Defense Technology Changsha Hunan China School of Microelectronics Xidian University Xi'an Shanxi China

ISBN: (纸本)9781424435432;9781424435449

The effect of quantum capacitance (QC) on the switching speed in T-CNFETs (Tunneling Carbon Nanotube Field Effect Transistors) is investigated with simulation using NEGF (Non-Equilibrium Green's Function) formalism. Firstly, based on the analytical expression of SS, a quantitative study of the source/drain leads doping level is made to obtain an averaged inverse subthreshold slope(SS) as small as possible. And then the impact of QC on the gate control, thus on SS, is studied. Lastly, for the first time, approaches for restricting the impacts of QC are investigated, such as tuning the drain-source bias condition or CNT diameter which are governed by the analytical expression presented at the end of this paper. The modeling results reveal that the QC in T-CNFET has a negative impact on both the SS and on-current, and such impact could be restricted effectively with a proper choice of drain-source voltage and CNT chirality.

关键词： Quantum capacitance Doping Voltage Semiconductor process modeling Electrons Tunneling CNTFETs Green's function methods Iron PIN photodiodes

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A distributed approach to consistent order delivery of concurrent events in asynchronous DVEs

ICETC 2010 - 2010 2nd International Conference on Education ...

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ICETC 2010 - 2010 2nd International Conference on Education Technology and Computer 2010年 4卷 V495-V498页

作者： Zhou, Hangjun Zhang, Wei Peng, Yuxing Li, Sikun Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha Hunan 410073 China Department of Information Management Hunan College of Finance and Economics Changsha Hunan 410205 China

ISBN: (纸本)9781424463688

In large-scale asynchronous distributed virtual environments(DVEs), one of the difficult problems is to deliver the concurrent events in a consistent order at each node. Generally, the previous consistency control approaches can be classified into two categories: causal order and time stamped order. However, causal order approaches can merely preserve the cause-effect relation of events and time stamped order approaches seem intrinsically complex to be used in serverless large-scale asynchronous DVEs. In this paper, we proposed a novel distributed algorithm to identify the concurrent events and preserve the consistent order delivery of them at different nodes. Simulation studies are also carried out to compare the performance of this algorithm with that of the previous ones. The results show that the new algorithm can effectively deliver the concurrent events in consistent order at each node and is more efficient than the previous algorithms in large-scale asynchronous DVEs. © 2010 IEEE.

关键词： Virtual reality

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