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检索条件"机构=National Key Laboratory for Parallel and Distributed Processing"

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A Virtual Machine Server Aggregation Algorithm Based on Hierarchical Clustering

A Virtual Machine Server Aggregation Algorithm Based on Hier...

引用

International Conference on parallel and distributed Systems (ICPADS)

作者： Feng Huang Dongsheng Li National Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha China

Combining virtual machine technology and network computing technology will be able to effectively aggregate the widely distributed heterogeneous and autonomous resources in the Internet. This paper proposes a virtual machine server aggregation algorithm, called DVSA, based on hierarchical clustering method for virtual computing environment. According to network latencies, the algorithm clusters virtual machine servers into groups. If servers in the same group are scheduled, the latencies between virtual machines which host on these servers will be small, and the performance and stability of the distributed execution environment could be improved.

关键词： Virtual machining Clustering algorithms Network servers Web server Delay Computers Aggregates IP networks Clustering methods Processor scheduling

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Simulation and analysis of single-electron transistors with 1-dimension multiple islands

Simulation and analysis of single-electron transistors with ...

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IEEE Conference on Nanotechnology

作者： Bingcai Sui Yaqing Chi Hailiang Zhou Chao Zhang Liang Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

ISBN: (纸本)9781424448326

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. Based on the Monte Carlo (MC) and stable diagram method, the critical problems during simulating and analyzing the SETs with multi-islands are investigated, e.g. capacitance matrix, potential of the islands, the free energy and so on. Meanwhile, double-island SET is simulated and analyzed as an example of SETs with 1-D muti-islands in detail. For the first time, 3-D stable diagram is obtained, and some new phenomena are analyzed in the paper. And through analyzing the result it's shown that although SETs with 1-D muti-islands is more useful and powerful than SETs with single island, there inevitably exists many effects because of the coupling energy between the islands.

关键词： Analytical models Single electron transistors Tunneling Carbon nanotubes Capacitance Voltage Energy consumption Capacitors Very large scale integration Temperature

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Creating Virtual Networks for distributed Virtual Computing Environment

Creating Virtual Networks for Distributed Virtual Computing ...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Dongsheng Li Yixin Chen Feng Huang National Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha Hunan China

Virtual network is an important approach to support multiple legacy applications running unmodified in distributed virtual computing environments. A virtual networking approach called VirNet is proposed in this paper. VirNet can build multiple customized and isolated virtual networks simultaneously on the same physical hosts in the network, and it enables existing distributed applications written for LANs to run seamlessly on Internet. VirNet is designed completely in user space and requires no change to the kernel of operating systems. Experimental evaluation performed by a reference implementation shows that VirNet is efficient. The latency overhead caused by VirNet is very small and the bandwidth of VirNet is more than 85% of the available physical network bandwidth in both the LAN and emulated WAN environments.

关键词： Computer networks distributed computing Bandwidth IP networks Kernel Operating systems Performance evaluation Delay Local area networks Wide area networks

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Optimization techniques of on-chip memory system based on UltraSPARC architecture

Optimization techniques of on-chip memory system based on Ul...

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Anwen Huang Jun Gao Chaochao Feng Minxuan Zhang Key Laboratory of Science and Technology of National Defense of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China

It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary element of on-chip memory system is simulated by ModelSim and synthesized by Synopsys Design Complier with 90 nm standard cell library. Aimed at the potential limiting factor of improving the performance of memory hierarchy, corresponding optimization techniques of critical elements in memory system are explored finally.

关键词： System-on-a-chip Elliptic curve cryptography Hardware Costs Algorithm design and analysis Random access memory Clocks Registers Elliptic curves Protection

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Program Optimization of Array-Intensive SPEC2k Benchmarks on Multithreaded GPU Using CUDA and Brook+

Program Optimization of Array-Intensive SPEC2k Benchmarks on...

引用

International Conference on parallel and distributed Systems (ICPADS)

作者： Guibin Wang Tao Tang Xudong Fang Xiaoguang Ren National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

Graphic processing Unit (GPU), with many light-weight data-parallel cores, can provide substantial parallel computing power to accelerate several general purpose applications. Both the AMD and NVIDIA corps provide their specific high performance GPUs and software platforms. As the floating-point computing capacity increases continually, the problem of ``memory-wall'' becomes more serious, especially for array-intensive applications. In this paper, we optimize and implement two SPEC2k benchmarks mgrid and swim on multithreaded GPU using CUDA and Brook+. In order to reduce the pressure on off-chip memory, we make use of data locality in multi-level memory hierarchies and hide long memory access latency via double-buffers. To balance inter-thread parallelism and intra-thread locality, we further tune thread granularity for each kernel and empirically study the best equilibrium point for this problem. Flow control instruction can significantly impact the effective instruction throughput. Oriented to this problem, we introduce a diverge elimination technology to convert condition expression into computing operation. Through all the optimizations, we gain the speedup of 10×-34× to the CPU implementation on the GPUs of AMD and NVIDIA respectively. Finally, we summarize and compares the GPUs from AMD and NVIDIA in hardware and software.

关键词： parallel processing Application software Graphics Acceleration Software performance Delay Yarn Kernel Throughput Central processing Unit

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Program Optimization of Stencil Based Application on the GPU-Accelerated System

Program Optimization of Stencil Based Application on the GPU...

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International Symposium on parallel and distributed processing with Applications, ISPA

作者： Guibin Wang Xuejun Yang Ying Zhang Tao Tang XuDong Fang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

Graphic processing Unit (GPU), with many light-weight data-parallel cores, can provide substantial parallel computational power to accelerate general purpose applications. But the powerful computing capacity could not be fully utilized for memory-intensive applications, which are limited by off-chip memory bandwidth and latency. Stencil computation has abundant parallelism and low computational intensity which make it a useful architectural evaluation benchmark. In this paper, we propose some memory optimizations for a stencil based application mgrid from SPEC 2 K benchmarks. Through exploiting data locality in 3-level memory hierarchies and tuning the thread granularity, we reduce the pressure on the off-chip memory bandwidth. To hide the long off-chip memory access latency, we further prefetch data during computation through double-buffer. In order to fully exploit the CPU-GPU heterogeneous system, we redistribute the computation between these two computing resource. Through all these optimizations, we gain 24.2 x speedup compared to the simple mapping version, and get as high as 34.3 x speedup when compared with a CPU implementation.

关键词： Concurrent computing Application software Acceleration Yarn Delay distributed processing distributed computing Bandwidth parallel processing Prefetching

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Providing Responsiveness Requirement Based Consistency in DVE

Providing Responsiveness Requirement Based Consistency in DV...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Wei Zhang Hangjun Zhou Yuxing Peng Sikun Li National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China

Consistency and responsiveness are two important factors in providing the sense of reality in distributed Virtual Environment (DVE). However, it is not easy to optimize both aspects because of the trade-off between these two factors. As a result, most existing consistency maintenance methods ignored the responsiveness requirements, or just assumed a simple responsiveness requirement model which cannot meet the real need of DVE systems. In this paper, we first present a new responsiveness requirement model. The model can describe requirement satisfaction situation of each node. Base on this model, we propose a responsiveness requirement based consistency method. The method can adjust the utilization of time resource according to the requirements of different nodes and improve the overall responsiveness performance by at least 20%. Therefore, it provides a good support to increase the applicability of DVE systems.

关键词： Delay effects Virtual environment distributed processing Computer science Games Distance learning Electronic commerce Safety Research and development Real time systems

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SEMCS: A Precise Memory-Hierarchy Simulation Framework on parallel Full-System Simulator

SEMCS: A Precise Memory-Hierarchy Simulation Framework on Pa...

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WASE International Conference on Information Engineering, ICIE

作者： Junjie Wu Xiaohui Pan Guanghui Liu Xuejun Yang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

The memory wall problem makes researches on memory hierarchy more and more important. And in these researches, software simulation plays a significant role. To model the real runtime environment, full system simulators have been widely used. However, researchers are often perplexed by the precise problem when they run a parallel program on a full system multi-core simulator, especially in multiple configurations. Because the influence arising from operating system and the relative execution speed of parallel threads often make the performance of target programs uncertain. To solve the precise problem, this paper proposes a single execution multi-configuration simulation framework (SEMCS). Then we design and implement a Simics module, called trans-multicast using the SEMCS framework. Finally, we test a benchmark from SPEComp2001 on a four core processor in three memory hierarchy configurations. And the result has verified the effectiveness of the SEMCS framework.

关键词： Computational modeling Operating systems Testing Read-write memory Computer simulation Concurrent computing Yarn Cache memory Laboratories distributed processing

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Anode-ALM: An Aggregation-Based Application Level Multicast for Media Streaming

Anode-ALM: An Aggregation-Based Application Level Multicast ...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Feng Liu Yuxing Peng Xicheng Lu Parallel and Distributed Processing Laboratory School of Computer Science and Technology National University of Defense Technology Changsha China

Building application level multicast (ALM) for media streaming, we had better keep the invariability of source to-end delay (S2EDelay) of any node on the tree, so as to avoid delay jitter problem. In this paper, we proposed an aggregation-based ALM architecture, which aggregates the unstable nodes within a local area into a relative stable aggregation node Anode, and then builds tree by Anodes. Anode shields node's dynamicity inside and behaves as a stable one outside. To build the architecture, we first proposed an Anode structure by n-dimension anti-cube, and proposed a distributed algorithm to bind the logic view and physical view of an Anode dynamically by the differentiation and assimilation operations, which maintain the integrality of the logic view while the physical view changes dynamically. Experiment results indicate that our algorithm can keep the S2EDelay invariability of the built ALM tree effectively.

关键词： Streaming media Anodes Delay Stability Application software Jitter distributed algorithms Logic Internet Network topology

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Feedback-Based Energy-aware Scheduling Algorithm for Hard Real-time Tasks

Feedback-Based Energy-aware Scheduling Algorithm for Hard Re...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Dong-song Zhang Shi-yao Jin Tong Wu Hua-wei Li National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China Zhenjiang Watercraft College Jiangsu China

In this paper, we propose a new algorithm for dynamic voltage scaling (DVS) based on feedback control mechanism. Besides handling a periodic tasks, our algorithm significantly reduces the energy consumption of periodic tasks and consequently the energy consumption of the whole task set. The results show that, comparing to on-line dynamic voltage scaling (the best algorithm to our knowledge), our approach improves the energy savings by 10% on most task sets tested and by 5% on average.

关键词： Scheduling algorithm Dynamic voltage scaling Feedback control Processor scheduling Real time systems Energy consumption Voltage control Switches Heuristic algorithms Dynamic scheduling

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