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NH-CIL: A Nested Hierarchy Algorithm for Class Incremental Learning

NH-CIL: A Nested Hierarchy Algorithm for Class Incremental L...

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International Conference on computer Supported Cooperative Work in Design

作者： Mingyu Liu Yijie Wang Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Changsha Hunan P.R.China

ISBN: (纸本)9781728165981

Class incremental learning is widely applied in the classification scenarios as the number of classes is usually dynamically changing. However, the existing algorithms increase computational cost to implement class incremental learning in order to increase classification quality. In this paper, we propose a nested hierarchy algorithm based on OCSVM for class incremental learning, called NH-CIL. We reuse support vectors to eliminate redundant instances and catch the key ones to replace the whole model because of the generalization ability of OCSVM. When a new class arrives, NH-CIL adopts OCSVM on the new class and the old classes respectively to get the corresponding sketching supports vectors. Then NH-CIL reuses these two kinds of sketching support vectors to build a binary sub-classifier. These two steps are repeatedly nested to form a hierarchy classification model in a bottom-up manner while the number of classes increases. On the contrary, the testing phase is in a top-down manner. NH-CIL can be used as a flexible approach in the classification scenarios during the collaborative information processing. We conduct the experiments on 8 real-world benchmark datasets to compare NH-CIL with some other class incremental learning algorithms, e.g. SD-CIL, HS-CIL and OP-CIL. The experiment results show that NH-CIL averagely achieves more than 5.1%, 8.6% and 11.6% accuracy improvement and 39.8%, 24.7% and 12.6% efficiency improvement over SD-CIL, HS-CIL and OP-CIL, respectively.

关键词： Machine learning algorithms Computational modeling Heuristic algorithms Conferences Support vector machine classification Information processing Benchmark testing

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A Novel Deep Neural Network Model for Credit Risk Prediction of Chinese Farmers

A Novel Deep Neural Network Model for Credit Risk Prediction...

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IEEE International Conference on Data science in Cyberspace (DSC)

作者： Yalong Xie Aiping Li Ziniu Liu Kai Chen Hongkui Tu College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781665418164

China is a big agricultural county with more than 500 million rural population. In China, farmers usually loan from rural commercial banks or rural credit cooperatives. It is crucial for the national economic development and the improvement of people's standard of living that how to reasonably use funds to subsidize the agricultural population and reduce the risk of rural loans. At present, credit risk prediction of farmers mainly depends on the experience of experts in the business field, and there is little published research on using artificial intelligence methods to solve this problem. This paper presents a complete set of methods, including data collection, feature selection, etc. We propose a novel deep neural network model named DNN-CRP for credit risk prediction of Chinese framers. Experiments on an actual credit loan dataset of Chinese farmers are presented, and experimental results show that the comprehensive performance of the DNN-CRP model is better than current state-of-the-art models. It is believed that the DNN-CRP model proposed in this paper can help banks improve the efficiency of the credit loan business of farmers and reduce credit risks.

关键词： Deep learning Sensitivity Neural networks Sociology Predictive models Data collection Data models

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A Class of Fast and Accurate Multi-layer Block Summation and Dot Product Algorithms 18th

A Class of Fast and Accurate Multi-layer Block Summation a...

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18th IFIP WG 10.3 International Conference on Network and parallel Computing, NPC 2021

作者： He, Kang Barrio, Roberto Chen, Lin Jiang, Hao Liu, Jie Gu, Tongxiang Qi, Jin Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Department of Applied Mathematics University of Zaragoza ZaragozaE50009 Spain College of Computer National University of Defense Technology Changsha410073 China Institute of Applied Physics and Computational Mathematics Beijing100000 China

ISBN: (纸本)9783030935702

Basic recursive summation and common dot product algorithm have a backward error bound that grows linearly with the vector dimension. Blanchard [1] proposed a class of fast and accurate summation and dot product algorithms respectively called FABsum and FABdot, which trades off the calculation accuracy and speed by the block size. Castaldo [2] proposed a multi-layer block summation and dot product algorithm called SuperBlocksum and SuperBlockdot that can increase the accuracy while adding almost no additional calculations. We combine the idea of [1] with the multi-layer block structure to propose SuperFABsum (for "super fast and accurate block summation") and SuperFABdot (for "super fast and accurate block dot product"). Our algorithms have two variants, one is SuperFAB(within), the other is SuperFAB(outside). Our algorithms further improve accuracy and speed compared with FAB and SuperBlock. We conducted accuracy and speed tests on the high-performance FT2000+ processor. Experimental results show that SuperFABdot(within) algorithm is more accurate than FABdot and SuperBlockdot. Compared with FABdot, SuperFABdot(outside) algorithm can achieve up to 1.2 × performance speedup while ensuring similar accuracy. © 2022, IFIP International Federation for Information processing.

关键词： Artificial intelligence

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Power and performance analysis of the Graph 500 benchmark on the Single-chip Cloud computer

Power and performance analysis of the Graph 500 benchmark on...

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International Conference on Cloud Computing and Internet of Things (CCIOT)

作者： Zhiquan Lai King Tin Lam Cho-Li Wang Jinshu Su College of Computer National University of Defense Technology Changsha China Department of Computer Science The University of Hong Kong Hong Kong China National Key Laboratory of Parallel and Distributed Processing (PDL) Changsha China

ISBN: (纸本)9781479947638

The concerns of data-intensiveness and energy awareness are actively reshaping the design of high-performance computing (HPC) systems nowadays. The Graph500 is a widely adopted benchmark for evaluating the performance of computing systems for data-intensive workloads. In this paper, we introduce a data-parallel implementation of Graph500 on the Intel Single-chip Cloud computer (SCC). The SCC features a non-coherent many-core architecture and multi-domain on-chip DVFS support for dynamic power management. With our custom-made shared virtual memory programming library, memory sharing among threads is done efficiently via the shared physical memory (SPM) while the library has taken care of the coherence. We conduct an in-depth study on the power and performance characteristics of the Graph500 workloads running on this system with varying system scales and power states. Our experimental results are insightful for the design of energy-efficient many-core systems for data-intensive applications.

关键词： Kernel Benchmark testing computer architecture Programming Power measurement Computational modeling Runtime

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An effective control scheme to ensure real-time causal order in large-scale distributed interactive simulations

An effective control scheme to ensure real-time causal order...

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International Conference on Communication Software and Networks, ICCSN

作者： Hangjun Zhou Sha Fu Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha Hunan China Department of Information Management Hunan University of Finance and Economics Changsha Hunan China

When a large-scale distributed interactive simulation system is running on WAN, the sites usually disperse over a wide area in geography, which results in the simulation clock of each site is hardly to be accurately synchronized with that of other sites. The asynchronous clocks and large transmission latency on WAN bring on a problem for the large-scale simulations to preserve the real-time causal order delivery of received events at each site. In this article, we analyze the indirect way to compare the values of asynchronous simulation clocks at first, and then propose a novel scheme which can select the reconstructible causal control information for each message so as to ensure the causal ordering of events in real time. Experiments demonstrate that the scheme can weaken the effect of network latency, reduce the overhead of the transmission amount of control information and improve the causal order consistency in asynchronous distributed simulations.

关键词： Clocks Educational institutions

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A Fast Adversarial Sample Detection Approach for Industrial Internet-of-Things Applications

A Fast Adversarial Sample Detection Approach for Industrial ...

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International Workshop on Quality of Service

作者： Shigeng Zhang Yudong Li Shuxin Chen Xuan Li Jian Zhang School of Computer Science and Engineering Central South University College of Computer Science and Electronic Engineering Hunan University The Science and Technology on Parallel and Distributed Processing Laboratory (PDL) China

Adversarial attacks reveal the inherent vulnerability of deep neural networks, which face serious security issues for their security. Among them, the attack against the Deep Neural Network (DNN) application used in the Industrial Internet of Things (IIoT) is a key area in adversarial attacks. Adversarial examples generated by attackers by adding human-undetectable interference to legitimate examples may cause models to make wrong decision results, resulting in serious accidents. Many detection technologies have been proposed to mitigate the harm of adversarial examples to neural networks, among which the methods based on the difference of feature attribution between normal examples and adversarial examples show state-of-the-art detection performance, but they suffer from detection efficiency. In this work, we focus on improving the detection efficiency of the feature-attribution-based detection methods. We observe that there is still a significant difference in the feature attribution distribution of a normal image and an adversarial image even only some pixels in the image are processed, which can be verified by utilizing the Kolmogorov-Smirnov test. Based on this observation, we first adopt a variety of strategies to sample partial pixels in an image and then utilize the selected pixels to train a feature-attribution-based detector for detecting adversarial examples. Extensive experiments conducted on four datasets (MNIST, CIFAR-10, SVHN, CIFAR-100) against various attacks proved that the detection efficiency of the accelerated detection method is improved (for example, the average execution time was increased by 8.7 times on CIFAR-10) while the detection performance maintains state-of-the-art.

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The Robot Software Communications Architecture (RSCA): Embedded middleware for networked service robots 20

The Robot Software Communications Architecture (RSCA): Embed...

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20th IEEE International parallel and distributed processing Symposium, IPDPS 2006

作者： Hong, Seongsoo Lee, Jaesoo Eom, Hyeonsang Jeon, Gwangil Real-Time Operating Systems Laboratory School of Electrical Engineering and Computer Science Seoul National University Seoul 151-744 Korea Republic of Distributed Information Processing Laboratory School of Computer Science and Computer Engineering Seoul National University Seoul 151-744 Korea Republic of Department of Computer Engineering Korea Polytechnic University 2121 Jungwang-Dong Siheung-Si Gyunggi-Do 429-793 Korea Republic of

ISBN: (纸本)1424400546

In this paper, we present a robot middleware technology named Robot Software Communications Architecture (RSCA) for its use in networked home service robots. The RSCA provides a standard operating environment for the robot applications together with a framework that expedites the development of such applications. The operating environment is comprised of a real-time operating system, a communication middleware, and a deployment middleware. Particularly, the deployment middleware supports the reconfiguration of component-based robot applications including installation, creation, start, stop, tear-down, and un-installation, In designing RSCA, we have adopted a middleware called SCA from the software defined radio domain and extend it since the original SCA lacks the real-time guarantees and appropriate event services. We have fully implemented RSCA and performed measurements to quantify its run-time performance. Our implementation clearly shows the viability of RSCA. © 2006 IEEE.

关键词： Middleware

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NUMA-aware FFT-based Convolution on ARMv8 Many-core CPUs

NUMA-aware FFT-based Convolution on ARMv8 Many-core CPUs

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IEEE International Conference on Big Data and Cloud Computing (BdCloud)

作者： Xiandong Huang Qinglin Wang Shuyu Lu Ruochen Hao Songzhu Mei Jie Liu Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China School of Computer Science National University of Defense Technology Changsha China University of Pittsburgh Pittsburgh USA

Convolutional Neural Networks (CNNs), one of the most representative algorithms of deep learning, are widely used in various artificial intelligence applications. Convolution operations often take most of the computational overhead of CNNs. The FFT-based algorithm can improve the efficiency of convolution by reducing its algorithm complexity, there are a lot of works about the high-performance implementation of FFT-based convolution on many-core CPUs. However, there is no optimization for the non-uniform memory access (NUMA) characteristics in many-core CPUs. In this paper, we present a NUMA-aware FFT-based convolution implementation on ARMv8 many-core CPUs with NUMA architectures. The implementation can reduce a number of remote memory access through the data reordering of FFT transformations and the three-level parallelization of the complex matrix multiplication. The experiment results on a ARMv8 many-core CPU with NUMA architectures demonstrate that our NUMA-aware implementation has much better performance than the state-of-the-art work in most cases.

关键词： Deep learning Recurrent neural networks Convolution computer architecture Complexity theory Convolutional neural networks Kernel

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A consistency algorithm for causal and totally ordered event delivery in DVE

A consistency algorithm for causal and totally ordered event...

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International Conference on computer science and Information Technology (CSIT)

作者： Hangjun Zhou Wei Zhang Yuxing Peng Sikun Li Department of Information Management Hunan College of Finance and Economics Changsha Hunan China Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha Hunan China

How to preserve causal and totally ordered event delivery is an important issue in real-time serverless DVE(distributed Virtual Environment). However, most of the related works are designed to maintain causal order merely or time stamped order with intensive computation and bandwidth overhead. In this paper, we proposed a novel distributed algorithm to maintain the before-and-after relationship between events, both causal and concurrent, of DVE at each individual node. Several simulation experiments are carried out to evaluate the performance of our algorithm and the results demonstrate that the algorithm is effective in preserving causal and totally ordered event delivery and more efficient than the previous algorithms.

关键词： Artificial neural networks Silicon Educational institutions

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A causality based dynamic message ordering for DVEs on Wide Area Network

A causality based dynamic message ordering for DVEs on Wide ...

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International Conference on Communication Software and Networks, ICCSN

Due to the large message transmission latency in distributed Virtual Environments(DVEs) on Wide Area Net-work(WAN), the effectiveness of causality consistency control of message ordering is determined by not only causal order of messages but also the real-timeness. If merely causal order is considered, the real-time property of DVEs may not be ensured because of the unlimited waiting time for the delayed messages. While if only real-timeness is emphasized, there may be too many delayed messages, which have to be discarded, to maintain the quality of causal message ordering. Therefore, a trade-off between the quality of causal order delivery and real-timeness is necessary for DVEs. In this article, a novel causality based message ordering approach is presented. In general, this new approach dynamically balances the demands of causal order delivery and real-timeness. Experiment results demonstrate the approach can enhance the quality of causality, while simultaneously keep the real-time property of DVEs.

关键词： Educational institutions

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