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International Symposium on parallel and distributed processing (IPDPS)

作者： Seongsoo Hong Jaesoo Lee Hyeonsang Eom Gwangil Jeon Real-Time Operation Systems Laboratory School of Electrical Engineering and Computer Science Seoul National University of Technology Seoul South Korea Distributed Information Processing Laboratory School of Computer Science and Computer Engineering Seoul National University of Technology Seoul South Korea Department of Computer Engineering Korea Polytechnic University Siheung Gyeonggi South Korea

ISBN: (纸本)9781424400546

In this paper, we present a robot middleware technology named robot software communications architecture (RSCA) for its use in networked home service robots. The RSCA provides a standard operating environment for the robot applications together with a framework that expedites the development of such applications. The operating environment is comprised of a real-time operating system, a communication middleware, and a deployment middleware. Particularly, the deployment middleware supports the reconfiguration of component-based robot applications including installation, creation, start, stop, tear-down, and un-installation. In designing RSCA, we have adopted a middleware called SCA from the software defined radio domain and extend it since the original SCA lacks the real-time guarantees and appropriate event services. We have fully implemented RSCA and performed measurements to quantify its run-time performance. Our implementation clearly shows the viability of RSCA

关键词： Embedded software computer architecture Middleware Service robots Application software Standards development Real time systems Operating systems Software radio Performance evaluation

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MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies

MBAPIS: Multi-Level Behavior Analysis Guided Program Interva...

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International Conference on parallel Architecture and Compilation Techniques (PACT)

作者： Hongwei Cui Yujie Cui Honglan Zhan Shuhao Liang Xianhua Liu Chun Yang Xu Cheng Engineering Reserach Center of Microprocessor & System Ministry of Education School of Computer Science Peking University Beijing National Key Laboratory for Multimedia Information Processing School of Computer Science Peking University Beijing

Understanding program behavior is crucial in computer architecture research, but the growing size of benchmarks makes analyzing and simulating entire programs increasingly challenging. In practice, researchers often select representative program intervals for analysis and testing. These intervals are different sections of continuous execution of a program. SimPoint is a well-known method for selecting representative intervals using hardware-independent information. However, when focusing on a specific microarchitecture study, it is desirable to select intervals that are more relevant to that study. For instance, intervals with more branch mispredictions are more appropriate for branch prediction studies. We refer to these intervals as “tailored intervals” for branch prediction studies. This paper presents a Multi-level Behavior Analysis guided Program Interval Selection (MBAPIS) for selecting tailored intervals. For a given microarchitecture study, the first level of MBAPIS uses hardware performance counters to prioritize selecting the intervals that exhibit clearer microarchitectural characteristics relevant to that study. The second level analyzes the processor performance bottlenecks to further select the intervals where the concerned microarchitecture design more strongly impacts performance. Finally, MBAPIS performs clustering analysis with the basic block information of each interval selected by the first two levels, and selects the representative intervals among them while preserving the diverse software behavior. Additionally, we present a general and extensible interval-replaying design to accurately re-execute selected intervals. The SPEC CPU2006 and CPU2017 benchmarks are used for evaluation. The results demonstrate that MBAPIS can select representative and tailored intervals for two typical microarchi-tecture studies and deliver accurate estimates of the concerned hardware events for all tailored intervals in each benchmark, with an average error rate of

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MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies 23

MBAPIS: Multi-Level Behavior Analysis Guided Program Interva...

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Proceedings of the 32nd International Conference on parallel Architectures and Compilation Techniques

ISBN: (纸本)9798350342543

Understanding program behavior is crucial in computer architecture research, but the growing size of benchmarks makes analyzing and simulating entire programs increasingly challenging. In practice, researchers often select representative program intervals for analysis and testing. These intervals are different sections of continuous execution of a program. SimPoint is a well-known method for selecting representative intervals using hardware-independent information. However, when focusing on a specific microarchitecture study, it is desirable to select intervals that are more relevant to that study. For instance, intervals with more branch mispredictions are more appropriate for branch prediction studies. We refer to these intervals as "tailored intervals" for branch prediction *** paper presents a Multi-level Behavior Analysis guided Program Interval Selection (MBAPIS) for selecting tailored intervals. For a given microarchitecture study, the first level of MBAPIS uses hardware performance counters to prioritize selecting the intervals that exhibit clearer microarchitectural characteristics relevant to that study. The second level analyzes the processor performance bottlenecks to further select the intervals where the concerned microarchitecture design more strongly impacts performance. Finally, MBAPIS performs clustering analysis with the basic block information of each interval selected by the first two levels, and selects the representative intervals among them while preserving the diverse software behavior. Additionally, we present a general and extensible interval-replaying design to accurately re-execute selected *** SPEC CPU2006 and CPU2017 benchmarks are used for evaluation. The results demonstrate that MBAPIS can select representative and tailored intervals for two typical microarchitecture studies and deliver accurate estimates of the concerned hardware events for all tailored intervals in each benchmark, with an average error rate of le

关键词： Benchmark

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Optimizing Batched Small Matrix Multiplication on Multi-core DSP Architecture

Optimizing Batched Small Matrix Multiplication on Multi-core...

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International Symposium on parallel and distributed processing with Applications, ISPA

作者： Xiaohan Zuo Chunhua Xiao Qinglin Wang Chen Shi College of Computer Science Chongqing University China Key Laboratory of Dependable Service Computing in Cyber Physical Society Ministry of Education China National Key Laboratory of Parallel and Distributed Computing National University of Defense Technology Changsha China Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

General Matrix Multiplication (GEMM) is a critical computational operation in scientific computing and machine learning domains. While traditional GEMM performs well on large matrices, it is inefficient in terms of data transfer and computation for small matrices. Many High-Performance Computing (HPC) tasks can be decomposed into large batches of small matrix multiplication operations. Multi-core Digital Signal Processors (DSPs) are commonly used to accelerate high-performance computing. We present a design for batched fusion small matrix multiplication (BFMM) tailored for multi-core DSP architecture. To address the inefficiencies and redundancy in storage and computational operations associated with batch small matrix multiplications, we designed several strategies. We design a matrix fusion concatenation strategy, an access coordination mechanism, and a mechanism for fragment aggregation. BFMM supports an efficient K-dimension multi-core parallelization strategy. The parameter constraint model makes BFMM highly portable. BFMM also includes a performance evaluation model that facilitates assessment and verification. Experimental results demonstrate that, compared to traditional GEMM (TGEMM) on multi-core DSP and traditional GEMM with concatenated data access (TGEMM Op), BFMM exhibits superior performance. For large batches of small matrices, our design achieves 1.21x to 18x higher performance than TGEMM Op on single-core DSP, while on multi-core DSP, it outperforms TGEMM Op by 1.14x to 18.1x.

关键词： Performance evaluation Scientific computing High performance computing Digital signal processors Redundancy Batch production systems Signal processing algorithms computer architecture Machine learning Matrix decomposition

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Scalable unbiased sampling method based on multi-peer adaptive random walk

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Ruan Jian Xue Bao/Journal of Software 2009年第3期20卷 630-643页

作者： Fu, Yong-Quan Wang, Yi-Jie Zhou, Jing National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China Staff Room of Computer Command Academy of the Corps of Engineers Xuzhou 221000 China

To deal with the scalable and fast unbiased sampling problems in unstructured P2P systems, a sampling method based on multi-peer adaptive random walk (SMARW) is proposed. In the method, based on the multi-peer random walk process, a set of provisional peers are selected as agents which start the sampling processes, by which the sampling process is speeded up with receiving a set of tunable number samples each time;Meanwhile, after receiving new samples earlier agents are replaced with these new samples which repeat the sampling process. With this simple replacement, it can be guaranteed with high probability that the system can reach the optimal load balance;furthermore, SMARW adopts an adaptive distributed random walk adjustment process to increase the convergence rate of the sampling process. A detailed theorical analysis and performance evaluation confirm that SMARW has a high level of unbiased sampling and near-optimal load balancing capability. © by Institute of Software, the Chinese Academy of sciences. All rights reserved.

关键词： Peer to peer networks

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Unlearnable 3D Point Clouds: Class-wise Transformation Is All You Need 38

Unlearnable 3D Point Clouds: Class-wise Transformation Is Al...

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38th Conference on Neural Information processing Systems, NeurIPS 2024

作者： Wang, Xianlong Li, Minghui Liu, Wei Zhang, Hangtao Hu, Shengshan Zhang, Yechao Zhou, Ziqi Jin, Hai National Engineering Research Center for Big Data Technology and System China Services Computing Technology and System Lab China Cluster and Grid Computing Lab China Hubei Engineering Research Center on Big Data Security China Hubei Key Laboratory of Distributed System Security China School of Cyber Science and Engineering Huazhong University of Science and Technology China School of Software Engineering Huazhong University of Science and Technology China School of Computer Science and Technology Huazhong University of Science and Technology China

Traditional unlearnable strategies have been proposed to prevent unauthorized users from training on the 2D image data. With more 3D point cloud data containing sensitivity information, unauthorized usage of this new type data has also become a serious concern. To address this, we propose the first integral unlearnable framework for 3D point clouds including two processes: (i) we propose an unlearnable data protection scheme, involving a class-wise setting established by a category-adaptive allocation strategy and multi-transformations assigned to samples;(ii) we propose a data restoration scheme that utilizes class-wise inverse matrix transformation, thus enabling authorized-only training for unlearnable data. This restoration process is a practical issue overlooked in most existing unlearnable literature, i.e., even authorized users struggle to gain knowledge from 3D unlearnable data. Both theoretical and empirical results (including 6 datasets, 16 models, and 2 tasks) demonstrate the effectiveness of our proposed unlearnable framework. Our code is available at https://***/CGCL-codes/UnlearnablePC. © 2024 Neural information processing systems foundation. All rights reserved.

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Improved conjugate residual algorithm for large symmetric linear systems

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Jisuanji Xuebao/Chinese Journal of computers 2006年第3期29卷 495-499页

作者： Liu, Jie Liu, Xing-Ping Chi, Li-Hua Hu, Qing-Feng National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha 410073 China Institute of Applied Physics and Computation Mathematics Beijing 100088 China

The conjugate residual (CR) algorithm is a Krylov subspace algorithm that can be used to obtain fast solutions for symmetric linear systems with very large and very sparse coefficient matrices. By changing the computation sequence in the CR algorithm, this paper proposes an improved Conjugate Residual (ICR) algorithm. The numerical stability of ICR algorithm is same as CR algorithm, but the synchronization overhead that represents the bottleneck of the parallel performance is effectively reduced by a factor of two. And all inner products of a single iteration step are independent and communication time required for inner product can be over lapped efficiently with computation time of vector updates. From the theoretical and experimental analysis it is found that ICR algorithm is faster than CR algorithm as the number of processors in creases. The experiments performed on a 64-processor cluster indicate that ICR is approximately 30% faster than CR.

关键词： parallel processing systems

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A Complexity-Reduced Block-Selective Algebraic Multigrid Method for Implicitly Coupled Velocity-Pressure System on High Performance computers

SSRN

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SSRN 2023年

作者： Liang, Yuechao Guo, Xiao-Wei Li, Chao Yuan, Fan Song, Min Zhang, Qingyang Chen, Xinhai Liu, Jie Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha410073 China Institute for Quantum Information State Key Laboratory of High Performance Computing College of Computer Science and Technology National University of Defense Technology Changsha410073 China School of Mathematics and Computational Sciences Xiangtan University Xiangtan411105 China College of Computer Science and Technology National University of Defense Technology Changsha410073 China

The implicitly coupled pressure-based algorithm is widely acknowledged for its superior convergence and robustness in solving incompressible flow problems. However, the increased expansion scale of equations and difficulty in solving the resulting equation system has limited the widespread use of the coupling algorithm. This paper presents an optimized block-SAMG method, referred to as Red-SAMG, to significantly reduce computational complexity and memory consumption. Our approach employs a parallel modified independent set algorithm, allowing each process to perform matrix coarsening individually. An aggressive coarsening strategy further reduces complexity to address larger-scale problems. We conducted numerical experiments on a serial two-dimensional backward-facing step case and a parallel three-dimensional tunnel between rod bundles in the reactor core problem. The results demonstrate that the Red-SAMG method with aggressive coarsening reduces solution time by 12\% on the backward-facing step case. For large-scale three-dimensional problems under the same parallel conditions, the Red-SAMG method shortens the solution time by 14\% compared to the existing SAMG method. The Red-SAMG method with aggressive coarsening further reduces solution time by 49\%. Our optimized Red-SAMG method effectively reduces the complexity of the linear system arising from the implicitly coupled algorithm. The aggressive coarsening strategy also represents a significant advancement in improving the computational efficiency of the SAMG method. © 2023, The Authors. All rights reserved.

关键词： Coarsening

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parallel 3D deterministic particle transport on Intel MIC architecture

Parallel 3D deterministic particle transport on Intel MIC ar...

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International Conference on High Performance Computing & Simulation (HPCS)

作者： Qinglin Wang Zuocheng Xing Jie Liu Xiaogang Qiang Chunye Gong Jiang Jiang Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China H.H. Wills Physics Laboratory University of Bristol Bristol UK Science and Technology on Space Physics Libratory Beijing China School of Microelectronics Shanghai Jiao Tong University Shanghai China

Single-node computation speed is essential in large-scale parallel solutions of particle transport problems. The Intel Many Integrated Core (MIC) architecture supports more than 200 hardware threads as well as 512-bit double precision float-point vector operations. In this paper, we use the native model of MIC in the parallelization of the simulation of one energy group time-independent deterministic discrete ordinates particle transport in 3D Cartesian geometry (Sweep3D). The implementation adopts both hardware threads and vector units in MIC to efficiently exploit multi-level parallelism in the discrete ordinates method when keeping good data locality. Our optimized implementation is verified on target MIC and can provide up to 1.99 times speedup based on the original MPI code on Intel Xeon E5-2660 CPU when flux fixup is off. Compared with the prior on NVIDIA Tesla M2050 GPU, the speedup of up to 1.23 times is obtained. In addition, the difference between the implementations on MIC and GPU is discussed as well.

关键词： computer architecture Microwave integrated circuits Graphics processing units Tin Computational modeling Legged locomotion Equations

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A partition filter network for joint entity and relation extraction

arXiv

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arXiv 2021年

作者： Yan, Zhiheng Zhang, Chong Fu, Jinlan Zhang, Qi Wei, Zhongyu School of Computer Science Shanghai Key Laboratory of Intelligent Information Processing Fudan University Shanghai China National University of Singapore Singapore School of Data Science Fudan University Shanghai China

In joint entity and relation extraction, existing work either sequentially encode task-specific features, leading to an imbalance in inter-task feature interaction where features extracted later have no direct contact with those that come first. Or they encode entity features and relation features in a parallel manner, meaning that feature representation learning for each task is largely independent of each other except for input sharing. We propose a partition filter network to model two-way interaction between tasks properly, where feature encoding is decomposed into two steps: partition and filter. In our encoder, we leverage two gates: entity and relation gate, to segment neurons into two task partitions and one shared partition. The shared partition represents inter-task information valuable to both tasks and is evenly shared across two tasks to ensure proper two-way interaction. The task partitions represent intra-task information and are formed through concerted efforts of both gates, making sure that encoding of taskspecific features is dependent upon each other. Experiment results on six public datasets show that our model performs significantly better than previous approaches. In addition, contrary to what previous work has claimed, our auxiliary experiments suggest that relation prediction is contributory to named entity prediction in a non-negligible way. The source code can be found at https://***/ Coopercoppers/PFN. Copyright © 2021, The Authors. All rights reserved.

关键词： Signal encoding

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