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Improving performance portability for GPU-specific Open CL kernels on multi-core/many-core CPUs by analysis-based transformations

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Frontiers of Information Technology & Electronic Engineering 2015年第11期16卷 899-916页

作者： Mei WEN Da-fei HUANG Chang-qing XUN Dong CHEN School of Computer National University of Defense Technology National Key Laboratory of Parallel and Distributed Processing

OpenCL is an open heterogeneous programming framework. Although OpenCL programs are func- tionally portable, they do not provide performance portability, so code transformation often plays an irreplaceable role. When adapting GPU-specific OpenCL kernels to run on multi-core/many-core CPUs, coarsening the thread granularity is necessary and thus has been extensively used. However, locality concerns exposed in GPU-specific OpenCL code are usually inherited without analysis, which may give side-effects on the CPU performance. Typi- cally, the use of OpenCL＇s local memory on multi-core/many-core CPUs may lead to an opposite performance effect, because local-memory arrays no longer match well with the hardware and the associated synchronizations are costly. To solve this dilemma, we actively analyze the memory access patterns using array-access descriptors derived from GPU-specific kernels, which can thus be adapted for CPUs by （1） removing all the unwanted local-memory arrays together with the obsolete barrier statements and （2） optimizing the coalesced kernel code with vectorization and locality re-exploitation. Moreover, we have developed an automated tool chain that makes this transformation of GPU-specific OpenCL kernels into a CPU-friendly form, which is accompanied with a scheduler that forms a new OpenCL runtime. Experiments show that the automated transformation can improve OpenCL kernel performance on a multi-core CPU by an average factor of 3.24. Satisfactory performance improvements axe also achieved on Intel＇s many-integrated-core coprocessor. The resultant performance on both architectures is better than or comparable with the corresponding OpenMP performance.

关键词： OpenCL Performance portability Multi-core/many-core CPU Analysis-based transformation

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Fast image matching algorithm based on affine invariants

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Journal of Central South University 2014年第5期21卷 1907-1918页

作者：张毅卢凯高颖慧 National Laboratory for Parallel and Distributed Processing(National University of Defense Technology) College of Computer National University of Defense Technology College of Electronic Science and Engineering National University of Defense Technology

Feature-based image matching algorithms play an indispensable role in automatic target recognition （ATR）. In this work, a fast image matching algorithm （FIMA） is proposed which utilizes the geometry feature of extended centroid （EC） to build affine invariants. Based on at-fine invariants of the length ratio of two parallel line segments, FIMA overcomes the invalidation problem of the state-of-the-art algorithms based on affine geometry features, and increases the feature diversity of different targets, thus reducing misjudgment rate during recognizing targets. However, it is found that FIMA suffers from the parallelogram contour problem and the coincidence invalidation. An advanced FIMA is designed to cope with these problems. Experiments prove that the proposed algorithms have better robustness for Gaussian noise, gray-scale change, contrast change, illumination and small three-dimensional rotation. Compared with the latest fast image matching algorithms based on geometry features, FIMA reaches the speedup of approximate 1.75 times. Thus, FIMA would be more suitable for actual ATR applications.

关键词： affine invariants image matching extended centroid robustness performance

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CWLP:coordinated warp scheduling and locality-protected cache allocation on GPUs

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Frontiers of Information Technology & Electronic Engineering 2018年第2期19卷 206-220页

作者： Yang ZHANG Zuo-cheng XING Cang LIU Chuan TANG National Laboratory for Parallel and Distributed Processing National University of Defense Technology

As we approach the exascale era in supercomputing, designing a balanced computer system with a powerful computing ability and low power requirements has becoming increasingly important. The graphics processing unit（GPU） is an accelerator used widely in most of recent supercomputers. It adopts a large number of threads to hide a long latency with a high energy efficiency. In contrast to their powerful computing ability, GPUs have only a few megabytes of fast on-chip memory storage per streaming multiprocessor（SM）. The GPU cache is inefficient due to a mismatch between the throughput-oriented execution model and cache hierarchy design. At the same time, current GPUs fail to handle burst-mode long-access latency due to GPU＇s poor warp scheduling ***, benefits of GPU＇s high computing ability are reduced dramatically by the poor cache management and warp scheduling methods, which limit the system performance and energy efficiency. In this paper, we put forward a coordinated warp scheduling and locality-protected（CWLP） cache allocation scheme to make full use of data locality and hide latency. We first present a locality-protected cache allocation method based on the instruction program counter（LPC） to promote cache performance. Specifically, we use a PC-based locality detector to collect the reuse information of each cache line and employ a prioritised cache allocation unit（PCAU） which coordinates the data reuse information with the time-stamp information to evict the lines with the least reuse possibility. Moreover, the locality information is used by the warp scheduler to create an intelligent warp reordering scheme to capture locality and hide latency. Simulation results show that CWLP provides a speedup up to 19.8% and an average improvement of 8.8% over the baseline methods.

关键词： Locality Graphics processing unit (GPU) Cache allocation Warp scheduling

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Memory access characterization of scientific applications on GPU and its implication on low power optimization

Memory access characterization of scientific applications on...

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2011 International Conference on Computational and Information Sciences, ICCIS 2011

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9780769545011

Following current IC design technology trend, modern GPUs integrate more and more processing cores, and the speed gap between processor and memory system becomes even larger. As the number of cores continually increases, the available bandwidth per core decreases correspondingly. Therefore, memory access performance has been one of the most critical bottlenecks for better performance. This paper analyzes the impact of memory system on performance and scalability for GPU with several scientific applications using a cycle-accurate simulator. Two observations we make are (1) that memory bandwidth has relatively greater impact on performance than memory latency, because the latter factor could be well hidden with tremendous concurrent executing threads supported in modern GPU architecture, and (2) that through examining the performance scalability of variable active cores, using the maximum hardware-supported cores may not bring in better performance, especially for the memory-intensive applications. In the end we suggest a better power-efficient exploitation of GPU is to make judicious concurrency-throttling based on the memory usage in application. © 2011 IEEE.

关键词： Graphics processing unit

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Scaling Internet services by LinuxDirector 4

Scaling Internet services by LinuxDirector

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4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

作者： Zhang, Wensong Jin, Shiyao Wu, Quanyuan National Laboratory for Parallel and Distributed Processing ChangshaHunan410073 China

ISBN: (纸本)0769505902

LinuxDirector is a software tool that directs network connections to multiple servers that share their workload, which can be used to build highly scalable and highly available services. LinuxDirector extends the TCP/IP stack of the Linux kernel to support three IP load balancing techniques, which can make parallel services of different kinds of server clusters to appear as a service on a single IP address. Four scheduling algorithms have been implemented to assign connections to different servers, and a simple distributed lock manager is provided for applications on different servers to access shared data consistently. Scalability is achieved by transparently adding or removing a node in the cluster and high availability is provided by detecting node or daemon failures and reconfiguring the system appropriately. This paper describes the design and implementation of LinuxDirector and presents several of its features including scalability, high availability, connection affinity and icmp handling. © 2000 IEEE.

关键词： Scalability

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MilkyWay-2： back to the world Top 1

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Frontiers of Computer Science 2014年第3期8卷 343-344页

作者： Xiangke LIAO Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

On the 41st Top500 list announced in June 2013, the MilkyWay-2 system produced by national University of Defense Technology （NUDT） in China won the first place with a LINPACK test result of 33.86 PFLOPS. It has been one and a half year since its predecessor, MilkyWay-1 （TH-1）, reached the same place for the first time. On the newest Top500 list published in November 2013, MilkyWay-2 continued to win the champion.

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The design of QoS management framework based on CORBA A/V STREAM architecture 4

The design of QoS management framework based on CORBA A/V ST...

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4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

作者： Chen, Xiaomei Lu, Xichen Wang, Huaimin National Laboratory of Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)0769505902

As distributed multimedia applications become more widely diffused, flexibility for QoS management is increasingly essential. We put forward a QoS management framework called QoSMF. In order to solve the heterogeneous problems and get more flexible and reusable characteristics, we implement the QoSMF model into the CORBA A/V STREAM architecture. With the QoSMF, we can easily change the QoS strategies and arithmetic without wholly reprogramming and redesigning for different types of applications. © 2000 IEEE.

关键词： Common object request broker architecture (CORBA)

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FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing 10

FPGA accelerating double/quad-double high precision floating...

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24th ACM International Conference on Supercomputing, ICS'10

作者： Dou, Yong Lei, Yuanwu Wu, Guiming Guo, Song Zhou, Jie Shen, Li National Laboratory for Parallel and Distributed Processing NUDT Changsha 410073 China

ISBN: (纸本)9781450300186

In this paper we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on 128-bit or even 256-bit floating-point number representation. This paper addresses the accuracy when performing LU decomposition on large-scale matrices. In future ExaScale computing environments, accuracy errors are expected to increase up to a level which leaves only 11 significant bits in the mantissa. This is caused by the required large amount of accumulation operations which are in the order of O(n 3). Using exact long fixed-point numbers instead of usual floatingpoint numbers in the accumulation process, leads to exact accumulation results with only one bit error, originated by the rounding in the last normalization step. We have developed two types of High Precision Multiplication and Accumulation (HP-MAC), for Double-Double (128 bits) and Quad-Double (256 bits) floating-point, respectively, and implemented them into FPGA devices. We propose a two-level RAM banks scheme to store and add long fixed-point numbers with minimized crucial data paths lengths. We also introduce a scheme of partial summation to enhance the pipeline throughput of MAC operations, by dividing the summation function into 4 partial operations, processed in 4 banks. To prove the concept, we prototyped six 128-bit HP-MAC units into a Xilinx Virtex-5 XC5VLX330 FPGA chip and performed LU decomposition. The experimental results show accuracy improvement of 10 to 24 bits, compared to a software approach with similar precision arithmetic. Moreover, our LU decomposition implementation, based on FPGA running at 133MHz, achieves 29X - 56X better performance and much lower power consumption compared to the use of a software-based library running on an Intel Core2 Quad Q8200 CPU at 2.33GHz. © 2010 ACM.

关键词： Field programmable gate arrays (FPGA)

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Anadem: A hybrid overlay network for content-based data distribution

Anadem: A hybrid overlay network for content-based data dist...

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15th International Conference on parallel and distributed Systems, ICPADS '09

作者： Zheng, Zhong Wang, Yi-Jie National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769539003

As an infrastructure for data distribution, overlay networks have to feature efficient routing and adequate robustness to achieve fast and accurate data distribution in the environment with node churn. Considering that the existing overlay networks mostly focus on single optimization objective and fail to ensure routing efficiency and robustness simultaneously, a hybrid overlay network for content-based data distribution - Anadem is proposed in this paper. Anadem achieves a better compromise between routing efficiency and robustness by combining the intercluster multiple structured topologies with the intra-cluster unstructured topologies. Anadem also provides mechanisms for dynamic concurrent cluster creation, cluster departure and load balance to make data distribution more adaptive to the dynamic network environment. Experimental results reveal that compared with existing overlay networks, Anadem can support fast and accurate content-based data distribution even when large amount of nodes fail in the system. © 2009 IEEE.

关键词： Overlay networks

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Communication-aware task partition and voltage scaling for energy minimization on heterogeneous parallel systems

Communication-aware task partition and voltage scaling for e...

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2011 12th International Conference on parallel and distributed Computing, Applications and Technologies, PDCAT 2011

作者： Wang, Guibin Song, Wei National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9780769545646

Heterogeneous parallel systems have become popular in general purpose computing and even high performance computing fields. There are many studies focused on harnessing heterogeneous parallel processing for better performance. However the energy optimization for heterogeneous system has not been well studied. Owing to the differences in performance and energy consumption, the energy optimization technique for heterogeneous system is different from the existing methods designed for homogeneous system. Besides typical voltage scaling method, reasonable task partitioning is also an essential method for optimizing energy consumption on heterogeneous systems. Through partitioning a data parallel task and mapping sub-tasks onto several processors, one could achieve better performance and reduced energy consumption. As the computation cost reduces with specific accelerators, the communication overhead becomes more prominent. Therefore, the task partition optimization should holistically consider the computation improvement and communication overhead to achieve higher energy efficiency. Typically, task partition and voltage scaling are not orthogonal and influence the effect of each other in the energy optimization problem. In order to harness both two knobs efficiently, this paper proposes an integer linear programming (ILP) based energy-optimal solution designed for heterogeneous system. We present a case study of optimizing MGRID benchmark on a typical CPU-GPU heterogeneous system. The experimental results demonstrate that the proposed method could exploit the heterogeneity in different processors and achieve improved energy efficiency. © 2011 IEEE.

关键词： Energy efficiency

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