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共 1147 条记录，以下是251-260 订阅

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Communication delay analysis based on network calculus

Communication delay analysis based on network calculus

引用

2010 2nd International Conference on Software Technology and Engineering, ICSTE 2010

作者： Lin, Yufei Xu, Xinhai Lin, Yisong National Laboratory for Parallel and Distributed Processing Computer School National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424486656

Network calculus is a promising theory for analyzing and modeling networks based on min-plus algebra. Using network calculus theory, we propose formulas of arrival curve and service curve for end-to-end communication, build the corresponding time model, and derive the communication delay formulas for two scenarios of the model respectively. Then we take fat tree topology, which is widely used in Infiniband interconnection, as an example to analyze the delay of one-to-all broadcast. This paper, as a groundwork, provides a new approach for the network researchers to delve communication delay in future researches. © 2010 IEEE.

关键词： Calculations

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Detecting null dereference with a game

Detecting null dereference with a game

引用

2012 International Conference on Information Technology and Software Engineering, ITSE 2012

作者： Chen, Jie National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology 410073 Changsha China

ISBN: (纸本)9783642345302

As one of the most dangerous and common software vulnerabilities, null dereference often leads to program crashes. In this chapter we propose a human computation method to detect null dereference in a "frog and bug" game. The purpose of the game is to utilize the rich distributed human resource to do the complex science work in a simple and pleasant way. Programs are transformed into visual puzzles first, and then the server collects information from the people playing the game. Finally the recorded metadata is translated back into the positions in the programs where null dereference may happen. The game has shown to be effective. © 2013 Springer-Verlag.

关键词： Computers

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Kernel fusion: An effective method for better power efficiency on multithreaded GPU

Kernel fusion: An effective method for better power efficien...

引用

2010 IEEE/ACM International Conference on Green Computing and Communications, GreenCom 2010, 2010 IEEE/ACM International Conference on Cyber, Physical and Social Computing, CPSCom 2010

作者： Wang, Guibin Lin, YiSong Yi, Wei National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9780769543314

As one of the most popular accelerators, Graphics processing Unit (GPU) has demonstrated high computing power in several application fields. On the other hand, GPU also produces high power consumption and has been one of the most largest power consumers in desktop and supercomputer systems. However, software power optimization method targeted for GPU has not been well studied. In this work, we propose kernel fusion method to reduce energy consumption and improve power efficiency on GPU architecture. Through fusing two or more independent kernels, kernel fusion method achieves higher utilization and much more balanced demand for hardware resources, which provides much more potential for power optimization, such as dynamic voltage and frequency scaling (DVFS). Basing on the CUDA programming model, this paper also gives several different fusion methods targeted for different situations. In order to make judicious fusion strategy, we deduce the process of fusing multiple independent kernels as a dynamic programming problem, which could be well solved with many existing tools and be simply embedded into compiler or runtime system. To reduce the overhead introduced by kernel fusion, we also propose effective method to reduce the usage of shared memory and coordinate the thread space of the kernels to be fused. Detailed experimental evaluation validates that the proposed kernel fusion method could reduce energy consumption without performance loss for several typical kernels. © 2010 IEEE.

关键词： Graphics processing unit

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SMP-SIM: An event-driven performance simulator for SMP

SMP-SIM: An event-driven performance simulator for SMP

引用

2012 International Conference on Systems and Informatics, ICSAI 2012

作者： Zhang, Xin Tang, Yuhua Lin, Yufei Xu, Xinhai Guo, Xiaowei Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467301992

Performance prediction for the high performance computer system is of great importance for designing, implementing, and optimizing system. As a widely used technique for predicting performance, simulation method attracts more and more attention from the research community. Based on analyzing the problems in the current performance simulation techniques, we present a key idea of the performance simulator for SMP system based on event-driven. We propose the framework of SMP-SIM and implement it based on MPICH2. The simulation results show that, our simulation technique has the advantages of high accuracy and simulation performance. © 2012 IEEE.

关键词： Forecasting

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Checkpoint selection in fault recovery based on byzantine fault model 4th

Checkpoint selection in fault recovery based on byzantine fa...

引用

4th International Conference on Computational Intelligence and Communication Networks, CICN 2012

作者： Xu, Xinhai Lin, Yufei National Laboratory for Parallel and Distributed Processing Computer School National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467329811

Nowadays, with the growth of the performance, the reliability problem of supercomputers becomes more and more serious. In order to complete an application with small fault recovery overhead, Checkpoint/Restart(C/R) methods are widely used. So far, the mainstream C/R methods are either based on Fail-Stop fault model or making the system(or program) do error detection before storing checkpoints, so they can ensure the correctness of every checkpoint. However, the faults occurring in the systems in real world are more accordant with the Byzantine fault model, and in order to pursue the higher practical performance, neither the system nor the program implements any fault detection mechanism. Consequently, there may be errors in the checkpoints. This paper studies the checkpoint selection problem that which checkpoint should be selected as the object of rolling back after system occurring failure, based on Byzantine fault model. We design a framework of checkpoint selection, and then, based on it, propose three checkpoint selection strategies: conservative strategy, aggressive strategy and statistical strategy. The simulation results show that: the conservative strategy shows its superiority when the error latent period is long, while the aggressive strategy behaves oppositely, the statistical strategy has a stable efficiency, only 50% more overhead compared to the ideal checkpoint selection when the checkpoint period is the half of mean time between faults. © 2012 IEEE.

关键词： Fault tolerance

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Program optimization of array-intensive SPEC2k benchmarks on multithreaded GPU using CUDA and brook+

Program optimization of array-intensive SPEC2k benchmarks on...

引用

15th International Conference on parallel and distributed Systems, ICPADS '09

作者： Wang, Guibin Tang, Tao Fang, Xudong Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9780769539003

Graphic processing Unit (GPU), with many lightweight data-parallel cores, can provide substantial parallel computing power to accelerate several general purpose applications. Both the AMD and NVIDIA corps provide their specific high performance GPUs and software platforms. As the floating-point computing capacity increases continually, the problem of "memory-wall" becomes more serious, especially for array-intensive applications. In this paper, we optimize and implement two SPEC2k benchmarks mgrid and swim on multithreaded GPU using CUDA and Brook+. In order to reduce the pressure on off-hip memory, we make use of data locality in multi-level memory hierarchies and hide long memory access latency via double-buffers. To balance inter-thread parallelism and intra-hread locality, we further tune thread granularity for each kernel and empirically study the best equilibrium point for this problem. Flow control instruction can significantly impact the effective instruction throughput. Oriented to this problem, we introduce a diverge elimination technology to convert condition expression into computing operation. Through all the optimizations, we gain the speedup of 10x-34x to the CPU implementation on the GPUs of AMD and NVIDIA respectively. Finally, we summarize and compares the GPUs from AMD and NVIDIA in hardware and software. © 2009 IEEE.

关键词： Graphics processing unit

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Power analysis and optimizations for GPU architecture using a power simulator

Power analysis and optimizations for GPU architecture using ...

引用

2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465408

As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus on the power analysis and optimizations for GPU architecture. The main contributions of this paper are: firstly, we establish a GPU power reserach platform, which is extended from an existing GPU simulator with several power models;secondly, we validate that, as the gap between shader core and memory speed becomes larger and larger, integrating more shader cores or enhancing running frequencies may not bring better performance, but results in higher energy consumption;thirdly, we show that traditional power optimization methods for CPUs, such as dynamic frequency scaling and concurrencythrottling, could be effectively applied on GPU architectures for better power efficiency, especially for memory-intensive applications. © 2010 IEEE.

关键词： Simulators

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Invalid pointer dereferences detection for CPS software based on extended pointer structures

Invalid pointer dereferences detection for CPS software base...

引用

2012 IEEE 6th International Conference on Software Security and Reliability Companion, SERE-C 2012

作者： Dong, Longming Dong, Wei Chen, Liqian National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769547435

Invalid pointer dereferences, such as null pointer dereferences, dangling pointer dereferences and double frees, are a prevalent source of software bugs in CPS software, due to flexible dereferencing pointers along various pointer fields. Existing tools have high overhead or are incomplete, thereby limiting their efficiency in checking the kind of CPS software with shared and mutable memory. In this paper, we present a novel extended pointer structure for detecting all invalid pointer dereferences in this kind of CPS software. We propose an invalid pointer dereferences detection algorithm based on the uniform transformation of abstract heap states. Experimental evaluation about a set of large C benchmark programs shows that the proposed approach is sufficiently efficient in detecting invalid pointer dereferences of CPS software with shared and mutable memory. © 2012 IEEE.

关键词： Program debugging

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Research on online failure prediction model and status pretreatment method for exascale system

Research on online failure prediction model and status pretr...

引用

3rd International Conference on Cyber-Enabled distributed Computing and Knowledge Discovery, CyberC 2011

作者： Zhou, Hao Jiang, Yanhuang National Laboratory for Parallel and Distributed Processing College of Computer Science National University of Defense Technology Changsha China

ISBN: (纸本)9780769545578

The reliability issue of Exascale system is extremely serious. Traditional passive fault-tolerant methods, such as rollback-recovery, can not fully guarantee system reliability any more because of their large executing overhead and long recovering duration. Active fault tolerance is expected to become another important fault-tolerant approach for Exascale system. Focusing on system failure prediction, which is one key step of active fault tolerance, we construct online failure prediction model and research on the effective method of system status pretreatment. In order to improve the accuracy and real-time feature of current methods, the proposed Improved Adaptive Semantic Filter (IASF) method processes the latest system logs regularly, filtering useless information out of them according to their semantics. Adopting the main idea of Vector Space Model (VSM), IASF method creates Event Vector corresponding to each log record. By calculating the cosine of vectorial angle, it evaluates the semantics correlation between different log records, and then executes temporal and spatial redundant filter considering the burst feature of log records. IASF method is insensitive to the type of system log and does not introduce any expert system or domain knowledge. The experiment result shows that system can eliminate about 99.6% of useless log records after executing IASF method. © 2011 IEEE.

关键词： Fault tolerance

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Error detection by redundant transaction in transactional memory system

Error detection by redundant transaction in transactional me...

引用

IEEE International Conference on Networking, Architecture and Storage

作者： Song, Wei Jia, Jia Peng, Yu-Xing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769545097

This paper addresses the issue of error detection in transactional memory, and proposes a new method of error detection based on redundant transaction (EDRT). This method creates a transaction copy for every transaction, and executes both original transactions and transaction copies on adequate processor cores, and achieves error detection by comparing the execution results. EDRT utilizes the data-versioning mechanism of transactional memory to achieve the acquisition of an approximate minimum error detection comparing data set, and the acquisition is transparent and online. At last, this paper validates the EDRT through 5 test programs, including 4 SPLASH-2 benchmarks. The experimental results show that, the average error detecting cost is about 3.68% relative to the whole program, and it's only about 12.07% relative to the transaction parts of the program. © 2011 IEEE.

关键词： Fault tolerance

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