Hidden terminal and collisions are well-known problems due to broadcasting nature of wireless network. In this paper, we address an efficient MAC protocol to evade the potential collisions caused by hidden terminals, ...
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Hidden terminal and collisions are well-known problems due to broadcasting nature of wireless network. In this paper, we address an efficient MAC protocol to evade the potential collisions caused by hidden terminals, where advanced phycical layer technique, full-duplex, is exploited to coordinate channel contention among nodes within two-hops range. Furhter-more, cooperative channel hopping(CCH) MAC is developed to improve the frequency efficiency by limiting the interference of hidden terminals and enabling a collision-free channel for further transmission. Basically, a fined channel hopping mechanism is proposed to avoid the continually interference and cooperative coordination is subjoined by the transmission of cyclic prefix. To the best of our knowledge, CCH-MAC validates the detection of subchannel contention on NI USRPs and evaluation via simulations shows that CCH-MAC achieves at least 35% throughput gain over FICA with a slightly loss in fairness.
With the development of high performance computing and Web 2.0 applications,unstructured data storage becomes more and more *** RDBMS isn't efficient for big data ***,RDBMS's scalability is ***' expansion ...
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With the development of high performance computing and Web 2.0 applications,unstructured data storage becomes more and more *** RDBMS isn't efficient for big data ***,RDBMS's scalability is ***' expansion often leads to a large scale of data *** paper designs and implements a high performance distributedkey-value database,which is distributed Stage *** servers are organized by a consistent hashing ring and distributed with the support of Zookeeper,a distributed service *** has a high single-node read/write *** route information is calculated by clients,which reduces the expense of expansion.
Coordination among users is an indispensable part in wireless networks for efficient medium access. Alone with the rapid increase of transmission rate, however, coordination time becomes insufferable. We present AFD, ...
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Coordination among users is an indispensable part in wireless networks for efficient medium access. Alone with the rapid increase of transmission rate, however, coordination time becomes insufferable. We present AFD, namely asymmetric full duplex, to achieve high coordination efficiency at nearly zero overhead. In AFD, channel contention is performed simultaneously with data transmission. We propose a 3D pipeline contention scheme where the contention process is divided into several parallel stages and executed in a pipelined manner in a 3D domain specified by time, frequency and spatial antenna. To mitigate the interference between the data packet and the contention signal, we adopt a singleton PN sequence as a contention pilot. AFD provides a novel network-scale full duplex capability. The performance is evaluated by both simulations and measurements in a testbed. AFD outperforms IEEE 802.11 significantly, i.e., the Jain's fairness index is around 0.95 with a throughput gain up to 120%.
Traditional wireless relay networks have large end-to-end time delay and low throughput because of the limit that it can't receive and forward at the same time. In this paper, we proposed IWFR: Immediate Wireless ...
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Traditional wireless relay networks have large end-to-end time delay and low throughput because of the limit that it can't receive and forward at the same time. In this paper, we proposed IWFR: Immediate Wireless Full-Duplex Relay which exploits the advantages of full-duplex to shorten the end-to-end time delay and improve the throughput. At the same time, we designed a new implicit acknowledgement mechanism, which can eliminate the ACK overheads and evidently improve the throughput of the relay. To implement IWFR, we also modified the full-duplex node architecture to make it support for immediate relay. Simulation shows that IWFR shortens the end-to-end time delay by 60% on average and improves the throughput to 240% of the original relay.
As a key technique in cloud computing, live virtual machine (VM) migration makes cloud computing elastic and renders more efficient resource scheduling. In many cases, live storage migration is also desirable. Compare...
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As a key technique in cloud computing, live virtual machine (VM) migration makes cloud computing elastic and renders more efficient resource scheduling. In many cases, live storage migration is also desirable. Compared to live VM migration, however, live storage migration is relatively slow. The speed gap between live VM migration and live storage migration may lead to poor Quality of Service (QoS) for cloud users. In this paper, we present a new resource migration scheme, called Decoupled Live Storage Migration (DLSM), which decouples the live storage migration from the live VM migration. DLSM can migrate the VM immediately, while data blocks actually required by the VM are moved on demand at later times. It achieves the on-demand data migration at the storage level without the need of modifying the hypervisor. The key contribution of DLSM is that it reduces the network traffic and speeds up the live storage migration, by completely eliminating iterative copy of dirty data over the network. This good property is achieved without relying on any tracking mechanism for dirty data blocks. Experimental evaluation demonstrates the efficiency and effectiveness of DLSM.
Coordination among users is an indispensable part in wireless networks for efficient access control. Alone with the rapid increase of the data transmission rate, however, coordination time becomes insufferable, even s...
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Coordination among users is an indispensable part in wireless networks for efficient access control. Alone with the rapid increase of the data transmission rate, however, coordination time becomes insufferable, even several times higher than that for data transmission. We present SIF, a signature-based frequency-domain contention mechanism to achieve high coordination efficiency with low overhead. In SIF, different user is assigned by a different PN sequence as a signature. A contending user issues its signature on some specific OFDM subcarriers and uses the binary sequence of the ON/OFF states of all OFDM subcarriers to deliver the contend information. A signature-based detection method is proposed to detect the CVs of other nodes quickly and reliably. It is shown that, the collision probability of SIF is very low even in a large wireless networks, e.g., less than 0.2% with 100 users. Moreover, as SIF can complete the coordination within one slot in most cases, the throughput gain is up to 200% in comparison with 802.11.
Github facilitates the pull-request mechanism as an outstanding social coding paradigm by integrating with social media. The review process of pull-requests is a typical crowdsourcing job which needs to solicit opinio...
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The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event cha...
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The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.
In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture h...
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ISBN:
(纸本)9781479944156
In the paper, a new implementation of a 3GPP LTE standards compliant turbo decoder based on GPGPU is proposed. It uses the newest GPU-Tesla K20c, which is based on the Kepler GK110 architecture. The new architecture has more powerful parallel computing capability and we use it to fully exploit the parallelism in the turbo decoding algorithm in novel ways. Meanwhile, we use various memory hierarchies to meet various kinds of data demands on speed and capacity. Simulation shows that our implementation is practical and it gets 76% improvement on throughput over the latest GPU implementation. The result demonstrates that the newest Kepler architecture is suitable for turbo decoding and it can be a promising reconfigurable platform for the communication system.
Fingerprint matching is a key procedure in fingerprint identification applications. The fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct reco...
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Fingerprint matching is a key procedure in fingerprint identification applications. The fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct recognition rate. Performance and cost are two critical factors when implementing minutia-based matching algorithms in most embedded applications. A low-cost, fully pipelined architecture for minutia-based fingerprint matching is proposed in this paper. A regular matching unit with a pipeline of 13 stages is designed as the core of the architecture, interfacing with a two-port RAM and a DDR3 controller. We implemented the whole architecture on a Xilinx FPGA board with the Virtex VII XC7VX485T chip. The matching unit can run with a frequency of 330 MHz on the chip, which leads the system to achieve a throughput of about 430000 fingerprints per second when processing typical datasets. The unit only occupies 568 slices, which is less than 1% of the available chip resources. The board only consumes 16 W of power when run. The architecture can gain about twice the throughput of the 2.93 GHz Intel Xeon5670 CPU at a low logic cost and power.
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