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Asia Communications and Photonics Conference and Exhibition (ACP)

作者： Yuxuan Wang Kunpeng Dai Bin Niu Yuechan Kong Tangsheng Chen Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing China Nanjing Electronic Devices Institute Nanjing China

Gallium Arsenide Schottky barrier diodes (GaAs SBDs) are widely used in terahertz (THz) applications. Quartz substrate has recently emerged as a promising platform for GaAs SBDs due to its intrinsically low permittivity under THz. Here, we demonstrate transferring of GaAs SBD active layers with electrodes to a quartz wafer using micro-transfer printing method. This allows as a versatile approach for future THz mixers and multipliers.

关键词： Printing Fabrication Electrodes Schottky diodes Gallium arsenide Schottky barriers Multichip modules

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Design of a 340 GHz GaN-Based Frequency Doubler with High Output Power

Design of a 340 GHz GaN-Based Frequency Doubler with High Ou...

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IEEE Asia-Pacific Conference on Antennas and Propagation (APCAP)

作者： Yiyuan Zheng Kai Zhang Kunpeng Dai Yuechan Kong Gang Lin Tangsheng Chen Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing China Nanjing Electronic Devices Institute Nanjing China

This paper presents a high-power 340 GHz frequency doubler based on GaN Schottky barrier diode (SBD) technology. The proposed frequency doubler consists of a pair of GaN SBDs chips, a quartz circuit, as well as the transition waveguides. To improve the power handling capabilities, a pair of GaN SBDs chips with six anodes in total is flip-chip mounted on the quartz circuit. The suspended microstrip line is employed in the circuit on quartz due to its low-attenuation characteristics at terahertz frequencies. To enhance the electrical performance of frequency doubler, low-loss transition structures are designed. The proposed frequency doubler shows a simulated output power of 300 mW with a conversion efficiency of 20% at 340 GHz.

关键词： Waveguide transitions Schottky diodes Filtering Schottky barriers Frequency conversion Scattering parameters Microstrip

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Nondestructive visualization of graphene on Pt with methylene blue surface modification

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science China Materials 2022年第10期65卷 2763-2770页

作者： He Kang Yanhui Zhang Yun Wu Shike Hu Jing Li Zhiying Chen Yanping Sui Shuang Wang Sunwen Zhao Runhan Xiao Guanghui Yu Songang Peng Zhi Jin Xinyu Liu State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information TechnologyChinese Academy of SciencesShanghai 200050China Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of SciencesBeijing 100049China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Device InstituteNanjing 210016China Microwave Devices and Integrated Circuits Department Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China

Efficient large-scale nondestructive quality assessment of graphene on Pt is essential to the in-depth growth research and practical applications of ***,we present a very simple method for directly observing the domains and defects in graphene on Pt using an ordinary optical *** was achieved by modifying graphene on Pt using methylene blue(MB).Because the chemical activities of graphene and Pt surface differ significantly,the adsorption and reaction of MB on graphene and platinum surface *** can determine the distribution of graphene crystal domains and defects by comparing the colors in the optical *** addition,this characterization method causes no obvious damage to the Pt substrate and ***,it does not affect the recycling of the substrate or the subsequent characterization or application of *** study provides a nondestructive method for measuring the quality of graphene on Pt on a large scale,as well as a reference for the characterization and doping of other two-dimensional materials.

关键词： graphene Pt nondestructive visualization surface modification methylene blue

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Suppression of Short Channel Effects in Hydrogen- Terminated Diamond MISFETs Using an Al2 O3 / HfO2 Stacked Passivation Layer

Suppression of Short Channel Effects in Hydrogen- Terminated...

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Asia-Pacific Conference on Microwave

作者： Zhihao Chen Xinxin Yu Shuman Mao Yu Fu Jianjun Zhou Yuechan Kong Tangsheng Chen Ruimin Xu Bo Yan Yuehang Xu School of Electronic Science and Engineering University of Electronic Science and Technology of China Chengdu China Research Center of Integrated Circuits and Systems Yangtze Delta Region Institute (Huzhou) University of Electronic Science and Technology of China Huzhou China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute Nanjing China

The short channel effects (SCEs) are mainly caused by the generated insufficient depletion region under the gate, which can severely reduce the reliability of devices. In this paper, the effects are analyzed by the proposed metal-insulator-semiconductor (MIS) capacitance model and can be suppressed by the applied high-k upper passivation layer (UPL). To verify the proposed model, the hydrogen-terminated diamond MIS field-effect transistors (C-H diamond MISFETs) with a 40-/100-$\mathrm{nm} \,\mathrm{Al}_{2} \mathrm{O}_{3} / \mathrm{HfO}_{2}$ stacked passivation layer were fabricated. Benefiting from the 100 -nm-thick HfO 2 UPL, the SCEs are suppressed and a high on/off ratio of $\sim 1 \times 10^{9}$ is achieved in the C-H diamond MISFET even a low aspect ratio of 7.5 for the first time. A cut-off frequency (${f}_{\mathrm{T}})$ of 6.1GHz and maximum oscillation frequency $\left(f_{\max }\right.$) of 11.1GHz were also obtained. The above results indicate that C-H diamond MISFETs with a high-k UPL in this work are promising in the high reliability and high frequency applications.

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Design of a RF Doherty Power Amplifier Based on Handset Application

Design of a RF Doherty Power Amplifier Based on Handset Appl...

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International Conference on Microwave and Millimeter Wave technology Proceedings

作者： Yujie Tang Yingjie Zhou Hao Zhou Lei Yang Yuan Zheng Yufeng Guo Yi Zhang College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China Nanjing GuoBo Electronics Co. Ltd Nanjing China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing China State Key Laboratory of Millimeter Waves Nanjing China

A Doherty Power Amplifier (PA) with high efficiency and high linearity that can be used in smart communication devices such as mobile phones in the sub-6GHz frequency band is proposed. This Doherty PA uses the InGaP/GaAs hetero-junction bipolar transistor (HBT) process. Compared with the traditional Doherty PA, the PA in this paper combines the choke inductance of the output collector and the phase compensation circuit with the output circuit of the Doherty PA respectively, which reduces the number of components required for matching. From the simulation, when the power supply voltage of the Doherty power amplifier is 4.2V, the operating frequency is 3.5GHz and the output power is 26.5dBm, the power added efficiency (PAE) reaches 34.5%, at the same time when using a 10MHz bandwidth LTE-3GPPFDD modulated signal the Adjacent Channel Power Ratio (ACPR) below to -35dBc.

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Blind Calibration Algorithm for Time-interleaved Analog-to-Digital Conversion System

Blind Calibration Algorithm for Time-interleaved Analog-to-D...

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International Conference on Microwave and Millimeter Wave technology Proceedings

作者： Ziqian Jiang Jie Xu Xiaopeng Li Youtao Zhang Changchun Zhang Yufeng Guo Yi Zhang College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China Nanjing GuoBo Electronics Co. Ltd Nanjing China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing China State Key Laboratory of Millimeter Waves Nanjing China

This paper presents a blind calibration algorithm for a multi-channel time-interleaved analog-to-digital conversion system implemented in MATLAB/simulink. The behavior level simulation of the calibration system is carried out. The simulation results show that the signal-to-noise ratio (SNR), signal-to-noise-distortion ratio(SNDR), and spurious-free dynamic range (SFDR) of the signal corrected by the calibration system are greatly improved, which lays a solid foundation for the subsequent digital circuit design. Behavioral simulations are presented for a 4-channel 10-bit TI-ADC in order to verify the effectiveness of the proposed method. Using the introduced calibration technique, SFDR increased by 33 dB on average.

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6-inch GaN/Si CMOS 1P2M monolithic Heterogeneous Process and Platformed Devices 21

6-inch GaN/Si CMOS 1P2M Monolithic Heterogeneous Process and...

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21st China International Forum on Solid State Lighting and 10th International Forum on Wide Bandgap Semiconductors, SSLCHINA: IFWS 2024

作者： Du, Wen-Zhang He, Han-Zhao Fan, Wen-Qi Wang, Zhuang Yang, Xiao-Dong Liang, Jiao Zhang, Qing-Chun Ma, Hong-Ping Ma, Wang Yuan, Li Zhou, Jia-Wan Wang, Tao Cai, Shu-Jun Qian, Cheng Zhang, Guang-Sheng Fu, Xiao-Jun Zhou, Hong Li, Hai-Ou Yang, Hong-Qiang Cheng, Jun-Ji Li, Liang Huang, Wei Zhang, D.W. School of Microelectronics Fudan University Shanghai200433 China School of Academy for Engineering & Technology Fudan University Shanghai200433 China Genettice Co. LTD Qingdao266200 China National Key Laboratory of Integrated Circuits and Microsystems Wuxi214035 China National Key Laboratory of Integrated Circuits and Microsystems Chongqing400060 China School of Microelectronics Xidian University Xi'an710071 China Guilin University of Electronic Technology Guilin541004 China University of Electronic Science and Technology of China Chengdu610054 China School of Electronic Information Engineering Suzhou Vocational University Suzhou215104 China

ISBN: (纸本)9798331541149

To solve problems of parasitic effects in interconnects, low reliability, and three-dimensional stress associated with 3D heterogeneous and stacking of small chips, the complete process and model research of a 6-inch 20V GaN/Si CMOS 1P2M/(111) Si monolithic heterogeneous integration in the paper is put forward at the first time. Innovations have been made in high-quality patterned selective epitaxy of GaN, compatibility of GaN/Si-based P-well CMOS processes, and platformed device design. This work has overcome several engineering challenges associated with the process integration of 6-inch Si CMOS IC and GaN IC chips, leading to the development of key devices such as (1) Si PMOS with a threshold voltage/current drive (VTH/IDS (forward)) of -0.7V, 2.5 mA/mm;(2) high-performance bulk silicon PN diodes with a forward voltage (VF) of about 0.72~0.79 V;(3) PNP and NPN silicon bipolar devices with β of approximately 260 and 300, respectively;(4) AlGaN/GaN HEMTs with VTH/IDS (forward) of -3V, 300-500 mA/mm. A prototype platform for heterogeneous integration processes, including Si CMOS and GaN processes, has been established. ©2024 IEEE.

关键词： Gallium nitride

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Low surface roughness gaas/si thin-film deposition using three-step growth method in mbe

Low surface roughness gaas/si thin-film deposition using thr...

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Asia-Pacific Conference on Silicon Carbide and Related Materials, APCSCRM 2019

作者： Wei, Wang Ben, Ma Hanchao, Gao Hailong, Yu Zhonghui, Li Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute Nanjing210016 China

ISBN: (纸本)9783035736427

Epitaxial GaAs-on-Si is an ideal material system for studying the physics of mismatched heteroepitaxy of a polar semiconductor layer grown on a non-polar substrate like silicon. Understanding and optimization of the initial nucleation of GaAs on silicon is the most crucial step in the success of GaAs/Si heteroepitaxy. Molecular beam epitaxy (MBE) technique has been used to deposit hetero-epitaxial GaAs thin-film on off-angle Si (100) substrate using the three-step growth method. After optimizing the growth parameters of low temperature (LT) buffer layer and high temperature (HT) epilayer, XRD analyses were performed. Characterization results of the GaAs (004) films which were not subjected to annealing, show a full-width half maximum (FWHM) of 760.1 arc sec and a root mean square (RMS) surface roughness of lower than 1 nm for a scanning area of 10 μm × 10 μm. © 2020 Trans Tech Publications Ltd, Switzerland.

关键词： Molecular beam epitaxy

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Directly integrated mixed-dimensional van der Waals graphene/perovskite heterojunction for fast photodetection

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InfoMat 2022年第8期4卷 82-92页

作者： Xiangshun Geng Peigen Zhang Jun Ren Guan-Hua Dun Yuanyuan Li Jialun Jin Chaolun Wang Xing Wu Dan Xie He Tian Yi Yang Tian-Ling Ren School of Integrated Circuits and Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua UniversityBeijingChina Shanghai Key Laboratory of Multidimensional Information Processing School of Communication and Electronic EngineeringEast China Normal UniversityShanghaiPeople's Republic of China

Mixed-dimensional(2D/3D)van der Waals(vdW)heterostructures made with complementary materials hold a lot of promise in the field of optoelectronic *** simple mechanical stacking,directly growing the single-crystal perovskite on 2D materials to construct a high-quality vdW heterojunction can better promote carrier *** this work,a monolithic integrated graphene/perovskite heterojunction device is fabricated by directly growing a single-crystal hybrid perovskite on monolayer *** to the strong inter-face coupling,the hybrid device achieves self-powering behavior and exhibits prominent photoresponse properties with a fast response speed of up to 2.05μ***,the responsivity and detectivity can be boosted to up to 10.41 A W1 and 4.65×10^(12)Jones under the actuation of3 V *** technique not only improves the device performance,but also provides an effective guideline for the development of next-generation directly integrated vdW optoelectronic devices.

关键词： CH_(3)NH_(3)PbBr_(3) graphene perovskite photodetectors van der Waals integration

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Process Development of Manifold Microchannels Cooling for Embedded Silicon Fan-Out (MMC-eSiFO) Package

Process Development of Manifold Microchannels Cooling for Em...

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Electronic Components and technology Conference (ECTC)

作者： Zhou Yang Yuchi Yang Peijue Lyu Jianyu Du Lang Chen Jin Kang Weihai Bu Kai Zheng Yikang Zhou Chi Zhang Wei Wang School of Integrated Circuits Peking University Beijing China Semiconductor Technology Innovation Center (Beijing) Corporation Beijing China School of Integrated Circuits Peking University National Key Laboratory of Science and Technology on Micro/Nano Fabrication Beijing China

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

As Moore’s Law tends to reach its limits, shrinking process technology nodes is no longer the most effective way to improve the performance of systems, and more attention is being focused on advanced packaging. Thermal dissipation as the main issue severely limits the reliability of 3D stacked modules. Embedded cooling is a feasible solution for interlayer cooling. However, the current manifold is incompatible with advanced packaging processes due to the footprint and manufacturing process. In this work, a manifold microfluidic cooling structure for embedded silicon Fan-Out (MMC-eSiFO) package is proposed and the thermal test vehicle (TTV) is designed, fabricated and tested. A silicon-based interposer is formed using a wafer bonding process by etching a cavity structure and a manifold channel on two silicon wafers, respectively. The large-area high-power chip is embedded into the cavity for effective cooling by the embedded microchannels. A high-density redistribution layer (RDL) is used to fan out the electrical I/O after fabricating the dielectric layer on the surface. In addition, multi-layer embedded liquid cooling of 3D package structure can be achieved by interposer with through silicon vias (TSVs). The use of a silicon-based interposer not only enables high aspect ratio TSVs and high-density RDL but also helps to reduce thermal stress in the package structure, as the interposer material is the same as the IC chip material. It is worth noting that the fabrication of the interposer and fan-out layer is wafer-level processing that enables production at scale. Multiple sets of cavities and manifold channels can be etched in a single package structure, making it compatible with chiplet technology. The package structure is expected to solve the thermal dissipation problem of multi-layer multi-chip assemblies.

关键词： Manifolds Fabrication Wafer bonding Three-dimensional displays Cooling Packaging Silicon

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