Two broadband detectors at W-band and D-band are analyzed and designed with low barrier Schottky diodes. The input circuit of the detectors is realized by low and high impedance microstrip lines, and their output circ...
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Two broadband detectors at W-band and D-band are analyzed and designed with low barrier Schottky diodes. The input circuit of the detectors is realized by low and high impedance microstrip lines, and their output circuit is composed of a radio frequency (RF) bandstop filter and a tuning line for optimum reflection phase of the RF signal. S-parameters of the complete circuit are exported to a circuit simulator for voltage sensitivity analysis. For the W band detectors, the highest measured voltage sensitivity is 11800 mV/mW at 100 GHz, and the sensitivity is higher than 2000 mV/mW in 80-104 GHz. Measured tangential sensitivity (TSS) is higher than -38 dBm, and its linearity is superior than 0.99992 at 95 GHz. For the D band detector, the highest measured voltage sensitivity is 1600 mV/mW, and the typical sensitivity is 600 mV/mW in 110-170 GHz. TSS is higher than -29 dBm, and its linearity is superior than 0.99961 at 150 GHz.
Ga- and N-polar AlGaN/GaN HEMTs were designed and epitaxially grown on Si- and C-face SiC substrates by MOCVD. The Capacitance-voltage characteristics of the two structures were investigated by C-V profile and drift-d...
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The frequency stabilities of lnP DHBTs in a broadband over 1 to 220 GHz are investigated. A hybrid π-topology small-signal model is used to accurately capture the parasitics of devices. The model parameters are extra...
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The frequency stabilities of lnP DHBTs in a broadband over 1 to 220 GHz are investigated. A hybrid π-topology small-signal model is used to accurately capture the parasitics of devices. The model parameters are extracted from measurements analytically. The investigation results show that the excellent agreement between the measured and simulated data is obtained in the frequency range 200 MHz to 220 GHz. The dominant parameters of the π-topology model, bias conditions and emitter area have significant effects on the stability factor K. The HBT model can be unconditionally stable by reasonable selection of the proper bias condition and the physical layout of the device.
W-band quartz based high output power fix-tuned doublers are analyzed and designed with planar Schot- tky diodes. Full-wave analysis is carried out to find diode embedding impedances with a lumped port to model the no...
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W-band quartz based high output power fix-tuned doublers are analyzed and designed with planar Schot- tky diodes. Full-wave analysis is carried out to find diode embedding impedances with a lumped port to model the nonlinear junction. Passive networks of the circuit, such as the low pass filter, the E-plane waveguide to strip transitions, input and output matching networks, and passive diode parts are analyzed by using electromagnetic simulators, and the different parts are then combined and optimized together. The exported S-parameters of the doubler circuit are used for multiply efficiency analysis. The highest measured output power is 29.5 mW at 80 GHz and higher than 15 mW in 76-94 GHz. The highest measured efficiency is 11.5% at 92.5 GHz, and the typical value is 6.0% in 70-100 GHz.
A 4H-SiC MOSFET with breakdown voltage higher than 3300 V has been successfully designed and fabricated. Numerical simulations have been performed to optimize the parameters of the drift layer and DMOSFET cell structu...
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A 4H-SiC MOSFET with breakdown voltage higher than 3300 V has been successfully designed and fabricated. Numerical simulations have been performed to optimize the parameters of the drift layer and DMOSFET cell structure of active area. The n-type epilayer is 33μm thick with a doping of 2.5 × 10^15 cm-3. The devices were fabricated with a floating guard ring edge termination. The drain current 1d= 5 A at Vg = 20 V, corresponding to vd = 2.5 v.
Ku-band GaN power transistor with output power over 100 W under the pulsed operation mode is pre- sented. A high temperature A1N nucleation together with an Fe doped GaN buffer was introduced for the developed GaN HEM...
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Ku-band GaN power transistor with output power over 100 W under the pulsed operation mode is pre- sented. A high temperature A1N nucleation together with an Fe doped GaN buffer was introduced for the developed GaN HEMT. The A1GaN/GaN hetero-structure deposited on 3 inch SiC substrate exhibited a 2DEG hall mobility and density of -2100 cm2/(V.s) and 1.0 x 10^13 cm-2, respectively, at room temperature. Dual field plates were introduced to the designed 0.25μm GaN HEMT and the source connected field plate was optimized for minimizing the peak field plate near the drain side of the gate, while maintaining excellent power gain performance for Ku-band application. The load-pull measurement at 14 GHz showed a power density of 5.2 W/mm for the fabricated 400 μm gate periphery GaN HEMT operated at a drain bias of 28 V. A Ku-band internally matched GaN power transistor was developed with two 10.8 mm gate periphery GaN HEMT chips combined. The GaN power transistor exhibited an output power of 102 W at 13.3 GHz and 32 V operating voltage under pulsed operation mode with a pulse width of 100 μs and duty cycle of 10%. The associated power gain and power added efficiency were 9.2 dB and 48%, respectively. To the best of the authors' knowledge, the PAE is the highest for Ku-band GaN power transistor with over 100 W output power.
In this paper, we investigate the influence of deep level defects on the electrical properties of Ni/4H-SiC Schottky diodes by analyzing device current-voltage(I-V) characteristics and deep-level transient spectra(DLT...
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In this paper, we investigate the influence of deep level defects on the electrical properties of Ni/4H-SiC Schottky diodes by analyzing device current-voltage(I-V) characteristics and deep-level transient spectra(DLTS). Two Schottky barrier heights(SBHs) with different temperature dependences are found in Ni/4 H-SiC Schottky diode above room temperature. DLTS measurements further reveal that two kinds of defects Z_(1/2) and Ti(c)~a are located near the interface between Ni and SiC with the energy levels of E_C-0.67 eV and E_C-0.16 eV respectively. The latter one as the ionized titanium acceptor residing at cubic Si lattice site is thought to be responsible for the low SBH in the localized region of the diode, and therefore inducing the high reverse leakage current of the diode. The experimental results indicate that the Ti(c)~a defect has a strong influence on the electrical and thermal properties of the 4 H-SiC Schottky diode.
A circuit topology for high-order subharmonic(SH) mixers is *** phase cancellation of idle frequency components,the SH mixer circuit can eliminate the complicated design procedure of idle frequency ***,the SH mixer ...
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A circuit topology for high-order subharmonic(SH) mixers is *** phase cancellation of idle frequency components,the SH mixer circuit can eliminate the complicated design procedure of idle frequency ***,the SH mixer circuit can achieve a high port isolation by phase cancellation of the leakage LO, RF and idle frequency *** on the high-order SH mixer architecture,a new Ka-band fourth SH mixer is analyzed and designed,it shows the lowest measured conversion loss of 8.3 dB at 38.4 GHz and the loss is lower than 10.3 dB in 34-39 *** LO-IF,RF-LO,RF-IF port isolation are better than 30.7 dB,22.9dB and 46.5 dB,respectively.
A Y-band frequency doubler is analyzed and designed with GaAs planar Schottky diode, which is flip-chip solded into a 50 μm thick quartz substrate. Diode embedding impedance is found by full- wave analysis with lumpe...
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A Y-band frequency doubler is analyzed and designed with GaAs planar Schottky diode, which is flip-chip solded into a 50 μm thick quartz substrate. Diode embedding impedance is found by full- wave analysis with lumped port to model the nonlinear junction for impedance matching without the need of diode equivalent circuit model. All the matching circuit is designed "on-chip" and the mul- tiplier is self-biasing. To the doubler, a conversion efficiency of 6.1% and output power of 5.4mW are measured at 214GHz with input power of 88mW, and the typical measured efficiency is 4.5% in 200 - 225 GHz.
TSV is a new technology to make interconnections between chips by creating vertical wafer-to-wafer vias. The application of ICP (inductively coupled plasma) dry etching to make TSV is discussed in this paper. Starting...
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