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Simulation, fabrication and characterization of 6500V 4H-SiC JBS diode

Simulation, fabrication and characterization of 6500V 4H-SiC...

引用

2013 International Conference on Mechatronics and Semiconductor Materials, ICMSCM 2013

作者： Huang, Run Hua Tao, Yong Hong Chen, Gang Bai, Song Li, Rui Li, Yun Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing China Nanjing Electronic Devices Institute Nanjing China

ISBN: (纸本)9783037859391

4H-SiC JBS diode with breakdown voltage higher than 6.5 kV has been successfully fabricated on 4H-SiC wafers with epitaxial layer. In this paper, the simulation, the fabrication, and the electrical characteristics of 4H-SiC JBS diode were reported. The drift layer thickness and doping are 55 μm and 9×1014 cm-3 respectively. 60 floating guard rings edge were fabricated as termination. The on-state voltage was 4 V at JF = 7A. © (2014) Trans Tech Publicutions, Switzerland.

关键词： Silicon carbide

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High-Performance Monolayer WS2 Field-effect Transistors on High-κ Dielectrics

High-Performance Monolayer WS2 Field-effect Transistors on H...

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The 6th International Conference on Nanoscience and technology, China 2015 (第六届中国国际纳米科学技术会议)

作者： Yang Cui Run Xin Zhihao Yu Yiming Pan Zhun-Yong Ong Xiaoxu Wei Junzhuan Wang Yun Wu Tangsheng Chen Yi Shi Baigeng Wang Yong-Wei Zhang Gang Zhang Xinran Wang National Laboratory of Solid State Microstructures School of Electronic Science and Engineeringand School of Physics Nanjing UniversityNanjing 210093P.R.China Institute of High Performance Computing 1 Fusionopolis Way138632Singapore Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic D

WS2 is an attractive two-dimensional semiconductor material for electronic and optoelectronic device applications due to its high phonon limited mobility compared to other transition metal *** measured field-effect mobility thus far,however,is much smaller than theoretical predictions,dominated by extrinsic factors including charge traps and impurities.

关键词： tungsten disulfide (WS2) transition metal dichalcogenides (TMDs) mobility interface

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Development of self-aligned process to decrease gate length in recessed SiC SIT

Development of self-aligned process to decrease gate length ...

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2014 International Conference on Manufacturing technology and Electronics Applications, ICMTEA 2014

作者： Chen, Gang Bai, Song Wang, Lin Tao, Yong Hong Liu, Haiqi Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing China Nanjing Electronic Devices Institute Nanjing China

ISBN: (纸本)9783038353287

Because of difficulty in deep ion implantation, the recessed gate structure has been favored in SiC SIT. In order to improve the frequency, it is a good method to decrease the gate length by eliminating the side wall ion implantation affection. We developed normally-on RF 4H-SiC SIT with high small signal gain. The effect of forming the side wall protection between the source mesa and the gate area was simulated. © (2014) Trans Tech Publications, Switzerland.

关键词： Silicon carbide

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Modeling Techniques for Graphene field-effect transistors

Modeling Techniques for Graphene field-effect transistors

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2015 International Conference on Communication Problem-Solving(ICCP)

作者： Haiyan Lu Yun Wu Shuai Huo Yuehang Xu Yuechan Kong Tangshen Chen Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute University of Electronic Science and Technology of China

ISBN: (纸本)9781467365451

This paper presents a hybrid-π equivalent circuit extract method for graphene field-effect transistors up to 66 GHz. Because the G-FET channel cannot be pinched off, the open and short structures are used to remove parasitic element of the pad. The intrinsic elements of the model parameters are extracted from measured S-parameters directly. The model is verified with experiments and simulations, and good agreements are observed. The model will provide some insights and guidance for the practical use of the GFETs and can be embedded in circuit simulation tools.

关键词： FET Modeling Techniques for Graphene field-effect transistors Graphene

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Research and Application of Ku-Band 200W AlGaN/GaN Power HEMT with Four Cells Internal Matching

Research and Application of Ku-Band 200W AlGaN/GaN Power HEM...

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IEEE Asia-Pacific Conference on Antennas and Propagation

作者： ShiChang Zhong Tangsheng Chen Chunjiang Ren Feng Qian Chen Chen Tao Gao National Key Laboratory of Monolithic Integrated Circuits and Modules P.O.Box 1601 Nanjing 210016 P.R.China Nanjing Electronic Devices Institute P. O.Box 1601 Nanjing 210016 P.R. China

ISBN: (纸本)9781479988983

In this paper, We research the AlGaN/GaN internal matching technology. Using in-house made four 20mm GaN Power HEMT transistors, the internal matching power HEMT demonstrates a pulse over f80W across the band of 13.7-14.5GHz, an output power more than 200W with a power gain of over 6dB, the power added efficiency (PAE) of 30.47% at 14 GHz, operated at 32V drain bias voltage (Vds) with the pulsed conditions at a duty of 1 0% with a pulse width of 100us. The package size excluding flange and leads is 17.4mm × *** is the highest output power in a 100W-class AlGaN/GaN HEMT in that such package at Ku-band to the best of our knowledge.

关键词： GaN HEMT PAE internal matching

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Design of single crystal silicon based RF MEMS switch with high contact force 3

Design of single crystal silicon based RF MEMS switch with h...

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3rd Asia-Pacific Conference on Antennas and Propagation, APCAP 2014

作者： Di, Mei Jing, Wu YuanWei, Yu PeiRan, Zhang Jian, Zhu NanJing Electronic Devices Institute NanJing210016 China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory NanJing210016 China

ISBN: (纸本)9781479943548

A metal contact RF MEMS switch based on single crystal silicon is presented in this article. Performance of the switch is demonstrated numerically in simulations. The mN-level contact and release forces are achieved. Pull-in voltage is calculated to be 40V. 1.5mN contact force and 1.2mN release force are achieved when actuation voltage is 50V. The isolation and insertion loss are better than -30.8dB and -0.09dB respective between DC and 10GHz. The fabrication process is presented as well. © 2014 IEEE.

关键词： Silicon wafers

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Transistors: Realization of Room‐Temperature Phonon‐Limited Carrier Transport in Monolayer MoS2by Dielectric and Carrier Screening (Adv. Mater. 3/2016)

引用

Advanced Materials 2016年第3期28卷

作者： Zhihao Yu Zhun‐Yong Ong Yiming Pan Yang Cui Run Xin Yi Shi Baigeng Wang Yun Wu Tangsheng Chen Yong‐Wei Zhang Gang Zhang Xinran Wang National Laboratory of Solid State Microstructures School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures Nanjing University Nanjing 210093 P. R. China Institute of High Performance Computing 1 Fusionopolis Way Singapore 138632 Singapore National Laboratory of Solid State Microstructures School of Physics Nanjing University Nanjing 210093 P. R. China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Device Institute Nanjing 210016 P. R. China

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Novel extraction method for small-signal equivalent circuit model of HEMTs based on vector fitting

Novel extraction method for small-signal equivalent circuit ...

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2014 IEEE International Conference on Communication Problem-Solving, ICCP 2014

作者： Wu, Yongzhi Ren, Kun Liu, Jun Wei, Cheng Haiyan, Lu Key Laboratory for RF Circuits and Systems of Ministry of Education Hangzhou Dianzi University Hangzhou310037 China Science and Technology on Monolithic Integrated Circuit and Modules Laboratory Nanjing Electronic Devices Institute Nanjing210016 China

ISBN: (纸本)9781479942466

A novel model method for III-V HEMTs small-signal model parameter extraction is presented in this work. All the model elements are directly derived from hot S-parameters, rather than cold S-parameters, by using vector fitting (VF) method The model renders excellent agreement with the measured and simulated data over 1 to 100 GHz, for a 2×150μm GaAs HEMT device manufactured in CETC-55 150nm GaAs pHEMT technology. © 2014 IEEE.

关键词： III-V semiconductors

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Design of a 340GHz GaAs monolithic integrated sub-harmonic mixer

Design of a 340GHz GaAs monolithic integrated sub-harmonic m...

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Asia-Pacific Conference on Microwave

作者： Ge Liu Bo Zhang Lisen Zhang Dong Xing Junlong Wang Yong Fan School of Electronic Engineering Universtity of Electronic Science and Technology of China Chengdu Sichuan China National Key Laboratory of Application Specific Integrated Circuits Hebei Semiconductor Research Institute Shijiazhuang China

ISBN: (纸本)9781479987689

In this paper, a 340GHz GaAs monolithic integrated sub-harmonic mixer based on planar Schottky diode is presented. The mixer circuit is fabricated on a 12um GaAs substrate included planar Schottky diode in a balanced configuration, the passive RF/LO and IF matching networks, filtering circuits, as well as transitions from waveguide to suspended micro-strip. Simulated results for the 340 GHz mixer achieved DSB conversion loss of 6.49dB at 306.4GHz when the LO pumped power was 5.96dBm at 165GHz. The conversion loss was less than 8dB from 290GHz to 355GHz.

关键词： Mixers Schottky diodes Gallium arsenide Power harmonic filters Electromagnetic waveguides Harmonic analysis Waveguide transitions

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The research of heterogeneous integration based on epitaxial layer transfer technology

The research of heterogeneous integration based on epitaxial...

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IEEE Conference on Electron Devices and Solid-State circuits

作者： LiShu Wu Yan Zhao Wei Cheng Zi Qian Huang Tangsheng Chen Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute Nanjing China

ISBN: (纸本)9781479923366

The present work describes the study and improvement of heterogeneous integration based on epitaxial layer transfer technique, which is used to separate III/V device structures from their substrate and transfer to the other substrate. Our work aims in the development of a new process for integration of GaAs devices with Si. It is based on low temperature bonding of the epitaxial layer transfer technology. Using this method, we demonstrate that GaAs PIN epitaxial layer on a 3 inch-diameter GaAs wafer is transferred to a silicon substrate. After the GaAs PIN epitaxial layer is transferred, the GaAs PIN devices on silicon are fabricated, besides the IV characteristic of GaAs PIN devices is unaffected by epitaxial layer transfer.

关键词： Epitaxial growth Gallium arsenide Substrates Lithography Performance evaluation Investment

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