Virtual network is an important approach to support multiple legacy applications running unmodified in distributed virtual computing environments. A virtual networking approach called VirNet is proposed in this paper....
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The paper presents a novel and synergistic system-level modeling approach based on aspect-oriented programming (AOP) and SystemC. A case study on a 128-bit binary floating-point adder is performed to demonstrate the m...
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ISBN:
(纸本)9781424429523
The paper presents a novel and synergistic system-level modeling approach based on aspect-oriented programming (AOP) and SystemC. A case study on a 128-bit binary floating-point adder is performed to demonstrate the modeling strength of the approach. The validation experiment shows the effectiveness of the proposed approach. This work constitutes a first attempt to employ AOP in modeling digital systems.
Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel pr...
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ISBN:
(纸本)9780769537825
Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been implemented in the IBM POWER6 microprocessor's fused multiply-add unit. The parallel prefix tree implemented on the IBM's EAC adder is a Kogge-Stone tree which has been chosen for its high performance and its low power consumption. Our comparative study highlights the main performance differences among fourteen different architecture configurations when targeting an FPGA EAC adder design. We focus on the area requirements and the critical path delay of these designs. Our experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.
Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel pr...
详细信息
Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been implemented in the IBM POWER6 microprocessor's fused multiply-add unit. The parallel prefix tree implemented on the IBM's EAC adder is a Kogge-Stone tree which has been chosen for its high performance and its low power consumption. Our comparative study highlights the main performance differences among fourteen different architecture configurations when targeting an FPGA EAC adder design. We focus on the area requirements and the critical path delay of these designs. Our experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.
This chapter presents a formalization of functional and behavioural requirements, and a refinement of requirements to a design for CoCoME using the Relational Calculus of Object and Component Systems (rCOS). We give a...
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If-conversion and predicated execution are widely adopted to eliminate branch misprediction penalty. Previous predication execution depends on compiler to generate explicit predicated instructions, In this paper, a tr...
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ISBN:
(纸本)3540296395
If-conversion and predicated execution are widely adopted to eliminate branch misprediction penalty. Previous predication execution depends on compiler to generate explicit predicated instructions, In this paper, a trace-based predicate mechanism named RIMP (Runtime IMplicit Predication) is discussed. The candidates of if-conversion will be identified during dynamic execution. Conventional trace cache has been modified to store RIMP traces, which include instructions both from fall-through and target block following the conditional branch. Hardware extension will add predication to RIMP trace automatically. With the help of RIMP, legacy applications can benefit from predication mechanism without recompiling source code. Simulation of RIMP implementation under diverse microarchitecture configurations is presented in the paper. Results have shown promising performance improvement. In general, RIMP with 64kB trace storage delivers an average 10.3% IPC improvement while actually speeding up the execution time by over 7%.
Experiments on transcription analysis have resulted huge genes expression data related with specific temporal and spatial information. These data can be used in new genes identification, analysis of genes express patt...
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Experiments on transcription analysis have resulted huge genes expression data related with specific temporal and spatial information. These data can be used in new genes identification, analysis of genes express patterns and the annotation of genomes, which may provide the reference standard for experiment design and result analysis of transcription experiments. Since the alternative splicing of eukaryotic genes have found to be universal and play an important role in physiology and pathology, systematic analysis of alternative splicing is becoming a new hotspot of functional genome research. Facing the immense and exponential increase of experimental express data and more new genomes getting sequenced, there is exigent of the strategy which can handle transcription sequences in large scale and automatic way. We elucidate the algorithms, the computing requirements and programs in different transcription sequences analysis systems and propose a strategy more suitable for large scale analysis of alternative splicing.
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