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International Conference on Multimedia and Signal processing

作者： Wen, Mei Ren, Ju Wu, Nan Su, Huayou Xun, Changqing Zhang, Chunyuan Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9780769543567

Real-time H.264 encoding of high-definition (HD) video (up to 1080p) is a challenge workload to most existing programmable processors. Instead, the novel programmable parallel processors such as stream processor, Graphic processor unit (GPU) and DSP offer a different and very promising technology for these demands. Thus, parallel computing for H.264 encoding on these processors is becoming a hot research point. It's challenged, because most emerging parallel processors focus on supporting Data Level parallel (DLP), while the dependency inherently existing in traditional H.264 encoding algorithm significantly restricts exploiting DLP. Facing the challenge, this paper presents data parallel processing methods for key modules of H.264 encoder which can eliminate the dependency restriction. The result shows that key modules including Intra-prediction, Inter-prediction and CAVLC achieve significant speedup on stream processor by using these data parallel processing methods.© 2011 IEEE.

关键词： parallel processing systems

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Approximating quantified SMT-solving with SAT

Approximating quantified SMT-solving with SAT

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International Conference on Secure Software Integration and Reliability Improvement Companion

作者： Fu, Xianjin Liu, Wanwei Li, Jing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769544540

Satisfiability Modulo Theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers and combination of theorems is a long-standing challenge, which has been a major bottleneck of practical application of SMT solvers in some fields. We reveal a decidable fragment of FOL involving quantifiers, which could not be solved by SMT solvers such as Z3, CVC3, etc., and show how to convert them into model checking problems. © 2011 IEEE.

关键词： Model checking

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Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA

Special-purposed VLIW architecture for IEEE-754 quadruple pr...

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29th IEEE International Conference on Computer Design 2011, ICCD 2011

作者： Lei, Yuanwu Dou, Yong Shen, Li Zhou, Jie Guo, Song National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781457719523

This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. Then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). The proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. The performance is improved through the explicitly parallel technology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. The experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A Compact Model for Multi-Island Single Electron Transistors

A Compact Model for Multi-Island Single Electron Transistors

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3rd IEEE International NanoElectronics Conference (INEC)/Symposium on Nanoscience and Nanotechnology in China

作者： Chi, Yaqing Zhong, Haiqin Zhang, Chao Fang, Liang National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan 410073 China

ISBN: (纸本)9781424435449

Multi-island single electron transistor is an important kind of the single electron transistor, which is convenient to realize the controllable room temperature operation. A novel semi-empirical compact model for the Multi-island single electron transistor is proposed. The new approach combines the orthodox theory of the single electron tunneling through single coulomb island and a novel empirical analysis procedure for the chain of multi coulomb islands to solve the current of the whole multi-island single electron transistor. The tunneling rates are calculated based on the orthodox theory for the single electron tunneling. The tunneling currents representing the first splitted peaks in the coulomb oscillation curves are calculated according to the assumption that the currents through all the coulomb islands are equal to each other at the stable states, while the currents representing the other splitted peaks are constructed and merged together according to the empirical analysis. The model is verified by the traditional SET simulator SIMON and shows much faster calculation speed than SIMON. Therefore, the novel compact model is suitable for the large scale MISET circuit simulation.

关键词： Single Electron Transistor Coulomb Island Coulomb Oscillation Splitted Peak

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Global EDF-based online, energy-efficient real-time scheduling in multi-core platform

Global EDF-based online, energy-efficient real-time scheduli...

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IEEE International Conference on Computer Science and Automation Engineering

作者： Zhang, Dongsong Chen, Fangyuan Jin, Shiyao National Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781424487257

As the energy consumption becomes increasingly prominent, how to meet time constraints while reducing the energy consumption as much as possible is a fundamental problem of the real-time scheduling in multi-core systems. Most of the existing energy-efficient scheduling approaches make assumptions on the properties of the scheduled tasks. In general, the properties of a task are unknown in advance until the task arrives. Thus, these approaches for deterministic tasks are not suitable to the general tasks. To schedule general tasks without prior knowledge of their properties, we propose an online and energy-efficient scheduling algorithm, based on Global Earliest Deadline First, for hard real-time tasks in multi-core processor platform. We propose a novel approach to decrease the execution frequency of tasks, and achieve a reasonable compromise between the time constraint and saved energy. This is ensured by utilizing the slack time of tasks and the dynamic voltage/frequency scaling techniques. The evaluation results show that our algorithm is well applied to the two types of dynamic voltage/frequency scaling techniques, and out-performs the Global EDF algorithm in terms of the saved energy. Specifically, our algorithm improves the saved energy of the Global EDF algorithm by at most 10% to 15% under real discrete dynamic voltage/frequency scaling levels. © 2011 IEEE.

关键词： Real time systems

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Survey of DHT topology construction techniques in virtual computing environments

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Science China(Information Sciences) 2011年第11期54卷 2221-2235页

作者： ZHANG YiMing 1,2,LU XiCheng 1,2 & LI DongSheng 1,21 national laboratory for parallel and distributed processing (PDL),Changsha 410073,China 2 School of Computer,national University of Defense Technology,Changsha 410073,China 1. National Laboratory for Parallel and Distributed Processing (PDL) Changsha 410073 China2. School of Computer National University of Defense Technology Changsha 410073 China

The Internet-based virtual computing environment (iVCE) is a novel network computing *** characteristics of growth,autonomy,and diversity of Internet resources present great challenges to resource sharing in *** DHT overlay (DHT for short) technique has various advantages such as high scalability,low latency,and desirable availability,and is thus an important approach to realizing efficient resource *** construction is a key technique for structured overlays that realizes basic overlay functions including dynamic maintenance and message *** this paper,we first introduce the traditional techniques of DHT topology construction,focusing mainly on dynamic maintenance and message routing of typical DHTs,DHT indexing techniques for complex queries,and DHT grouping techniques for matching domain *** then present recent advances in DHT topology construction techniques in iVCE taking advantage of the characteristics of Internet ***,we discuss the future of DHT topology construction techniques.

关键词： virtual computing environments DHT overlays topology construction distributed indexing flexible routing

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Storage allocation for redundancy scheme in reliability-aware cloud systems

Storage allocation for redundancy scheme in reliability-awar...

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2011 IEEE 3rd International Conference on Communication Software and Networks, ICCSN 2011

作者： Huang, Zhen Yuan, Yuan Peng, Yuxing National Laboratory of Parallel and Distributed Processing Computer Department National University of Defense Technology Changsha China

ISBN: (纸本)9781612844855

As the burst increasing of created and demand on information and data, the efficient solution on storage management is highly required in the cloud storage systems. As an important component of management, storage allocation scheme aims to use a low redundancy and also to achieve a high reliability. However, the two aims are hard to be unified. Considering the practical situation of Cloud systems, we propose a systematic storage allocation scheme to touch them both. And we also study the impact of many factors to the data reliability. © 2011 IEEE.

关键词： Information management

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Impact of imprecise programming of memristor on building hardware neural network

Impact of imprecise programming of memristor on building har...

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2nd Annual Conference on Electrical and Control Engineering, ICECE 2011

作者： Zhu, Xuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology ChangSha China

ISBN: (纸本)9781424481637

The application of memristor in building hardware neural network has accepted widespread interests, and may bring novel opportunities to neural computing. However, due to the limitation of programming precision, the conductance of memristor which represents stored information may deviate from theoretical value, and thus bring error to the neural computing results. In this paper, we analyze the impact of imprecise programming on building hardeware neural network through Monte Carlo simulation on feedback layer model. The results show that the fault-tolerance ability of neural network could well adapt to these errors, which further proves the potential of building neural networks using memristors. © 2011 IEEE.

关键词： Errors

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Fault recovery based on parallel recomputing in transactional memory system

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2011 International Conference on Electric and Electronics, EEIC 2011

作者： Song, Wei Jia, Jia National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9783642217647

This paper addresses the issue of fault recovery in transactional memory, and proposes a method of fault recovery based on parallel recomputing in transactional memory system. This method utilizes the data-versioning mechanism of transactional memory system to avoid the extra cost of state saving, rolls back a single transaction to avoid wasting the computing time of the fault-free transactions, and adopts the parallel recomputing method to reduce the cost of fault recovery. This paper applies this method to OpenTM programs, and proposes the implementation method of parallel recomputing in OpenTM. At last, this paper tests the performance of this method through a test program. The experimental results show that, compared with the fault recovery method of rolling back a single transaction, the parallel recomputing method in transactional memory system can execute the fault recovery quickly and accurately and the method has a well scalability. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： Fault tolerance

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LoGPX: A new communication model for message-passing programs

LoGPX: A new communication model for message-passing program...

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作者： Lin, Yufei Tang, Yuhua Guo, Xiaowei Xu, Xinhai National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781617823091

Message Passing Interface (MPI) is a de facto standard for writing high-performance message-passing applications on distributed memory systems. To design effective applications and predict the performance of future systems, an accurate communication model is needed. In this paper, we discuss the characteristics of current systems and MPI implementations, then propose a more complete communication model, named LoGPX, which synthetically captures the influences of MPI communication protocol, the invoking time of communication primitive, hardware resource and network contention. Based on the model, we obtain the condition that the message transmission cost reaches the infimum, and we show that if ignoring some factors of LoGPX model, it can be degenerated to several popular models such as LogP, LogGP, LoGPC and LogGPO. © 2011 Society for Modeling & Simu.

关键词： Message passing

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