With the growth of supercomputer's scale, the communication time during executing is increasing. This phenomenon arouses the architecture researchers' interests. In this paper, based on the fat-tree topology, ...
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ISBN:
(纸本)9781424465392;9781424465422
With the growth of supercomputer's scale, the communication time during executing is increasing. This phenomenon arouses the architecture researchers' interests. In this paper, based on the fat-tree topology, which is widely used in Infiniband, we present an one-to-all broadcast communication time model. After classifying applications into two kinds, we establish the ideal model and the bandwidth-limited model on the exponential-capacity binary fat-trees for the two kinds of applications. Through analyzing the models, we get the curves which describe the relationship between the communication time and the processor number. The conclusions we get in this paper can help system designers make better system design.
As one of the most popular accelerators, Graphics processing Unit (GPU) has demonstrated high computing power in several application fields. On the other hand, GPU also produces high power consumption and has been one...
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ISBN:
(纸本)9781424497799
As one of the most popular accelerators, Graphics processing Unit (GPU) has demonstrated high computing power in several application fields. On the other hand, GPU also produces high power consumption and has been one of the most largest power consumers in desktop and supercomputer systems. However, software power optimization method targeted for GPU has not been well studied. In this work, we propose kernel fusion method to reduce energy consumption and improve power efficiency on GPU architecture. Through fusing two or more independent kernels, kernel fusion method achieves higher utilization and much more balanced demand for hardware resources, which provides much more potential for power optimization, such as dynamic voltage and frequency scaling (DVFS). Basing on the CUDA programming model, this paper also gives several different fusion methods targeted for different situations. In order to make judicious fusion strategy, we deduce the process of fusing multiple independent kernels as a dynamic programming problem, which could be well solved with many existing tools and be simply embedded into compiler or runtime system. To reduce the overhead introduced by kernel fusion, we also propose effective method to reduce the usage of shared memory and coordinate the thread space of the kernels to be fused. Detailed experimental evaluation validates that the proposed kernel fusion method could reduce energy consumption without performance loss for several typical kernels.
As the system scales up continuously, the problem of power consumption for high performance computing (HPC) system becomes more severe. Heterogeneous system integrating two or more kinds of processors, could be better...
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As the system scales up continuously, the problem of power consumption for high performance computing (HPC) system becomes more severe. Heterogeneous system integrating two or more kinds of processors, could be better adapted to heterogeneity in applications and provide much higher energy efficiency in theory. Many studies have shown heterogeneous system is preferable on energy consumption to homogeneous system in a multi-programmed computing environment. However, how to exploit energy efficiency (Flops/Watt) of heterogeneous system for a single application or even for a single phase in an application has not been well studied. This paper proposes a power-efficient work distribution method for single application on a CPU-GPU heterogeneous system. The proposed method could coordinate inter-processor work distribution and per-processor's frequency scaling to minimize energy consumption under a given scheduling length constraint. We conduct our experiment on a real system, which equips with a multi-core CPU and a multi-threaded GPU. Experimental results show that, with reasonably distributing work over CPU and GPU, the method achieves 14% reduction in energy consumption than static mappings for several typical benchmarks. We also demonstrate that our method could adapt to changes in scheduling length constraint and hardware configurations.
This paper proposes a novel transactional memory design: conflict graph based hardware transactional memory. It allows two conflicting transactions both to commit if they do not violate the condition of serializabilit...
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This paper proposes a novel transactional memory design: conflict graph based hardware transactional memory. It allows two conflicting transactions both to commit if they do not violate the condition of serializability. Simulation results show that conflict graph based hardware transactional memory outperforms the state-of-art transactional memory system.
Many applications demand distributing data with different contents efficiently in the network environment with unreliable links and a high node churn. Existing approaches mostly focus on optimizing either efficiency o...
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Many applications demand distributing data with different contents efficiently in the network environment with unreliable links and a high node churn. Existing approaches mostly focus on optimizing either efficiency or robustness of data distribution, and fail to ensure both of them simultaneously. In this paper, we propose Semantic Cast - a content-based data distribution approach over self-organizing semantic overlay networks. Semantic Cast maintains a self-organizing semantic overlay based on view exchange (called Crowd). In Crowd, each node seeks neighbors with more similar interests by periodically exchanging its neighbor list (called view) with a chosen neighbor. Through these nodes' self-organizing behavior, various interest communities emerge in the overlay. For data distribution over Crowd, Semantic Cast adopts random walk to route data between interest communities, and adopts flooding to disseminate data inside the interested communities. The experimental results show that compared to existing approaches, Semantic Cast can support efficient content-based data distribution in the unreliable and highly dynamic network environment.
The influence of on-chip metal interconnections, power grids, heat sink together with packaging, and metal dummy fills on the transmission characteristics of a 2mm-long integrated dipole antenna pair has been investig...
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The influence of on-chip metal interconnections, power grids, heat sink together with packaging, and metal dummy fills on the transmission characteristics of a 2mm-long integrated dipole antenna pair has been investigated in this paper. These metal structures and placements have been classified and particular simulations are performed to explore the interference effects of neighboring various metal structures on transmission gain, phase, impedance and radiation pattern for on-chip dipole antenna pair. By virtue of the experimental results and analyses, several experiential linear expressions for antenna pair gain and phase in interference circumstances are obtained using numerical fit. A set of design rules is concluded accordingly for guiding on-chip antenna layout and design targeting wireless interconnect.
Many systems, such as Synthetic Aperture Radar (SAR) processing, two-dimensional image processing, 2d-FFT calculation, need access the row and column data of their matrix alternately. The DRAM memory should be used du...
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Many systems, such as Synthetic Aperture Radar (SAR) processing, two-dimensional image processing, 2d-FFT calculation, need access the row and column data of their matrix alternately. The DRAM memory should be used due to huge data in these systems. To improve the usage of memory bandwidth in such systems, this paper theoretically analyses the optimal window size to minimize the total number of opening/closing pages when performing in such instances by balancing the number of handling physical pages between row and column accesses. This paper presents a window-based optimal memory access method, and we implemented an FPGA-based SDRAM controller with eight simple ports, which is based on window accessing mechanism and supports commercialized SDARM. The experimental results show that the effective I/O bandwidth of external SDRAM using our window layout approach increases from 114.2MB/s of naive implementation to 730.2MB/s with over 6X speedup. In addition, we implemented two SAR processing systems with four FFT processing elements using our window-based SDRAM controller and Corner Turn method separately in FPGA chip. Results show window-based method can achieve a speedup of 2.6 compared to Corner Turn method.
Insects build architecturally complex nests and search for remote food by collaboration work despite their limited sensors, minimal individual intelligence and the lack of a central control system. Insets' co...
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ISBN:
(纸本)9781424472796
Insects build architecturally complex nests and search for remote food by collaboration work despite their limited sensors, minimal individual intelligence and the lack of a central control system. Insets' collaborations emerge as a response of the individual insects to Stigmergy. A sign-based model of Stigmergy to discuss collaboration is proposed in this paper where we picked up "sign" as a key notion to understand it. Therefore, sign is the link of all the components in a Stigmergic complex adaptive system. Based on this understanding, we propose a definition that reveals the nature of signs and exploit the significations and relationships carried by the notion of sign. Then, a sign-based model of Stigmergy is consequently reached, which captures the essentials of Stigmergy. A basic architecture of Stigmergy as well as its constituents are presented and discussed. At last, some applications of the model are discussed.
Single-electronic transistors (SETs) are considered as the attractive candidates for post-CMOS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room tempera...
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ISBN:
(纸本)9781424435432
Single-electronic transistors (SETs) are considered as the attractive candidates for post-CMOS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. A new simulation method-nSET, is introduced in this paper. Compared with other methods, nSET can simulate the SET device with 1-dimension multiple islands with high speed and accuracy. Through the comparison, it can be get that nSET is accurate and fast compared with the classical Monte Carlo (MC) simulator, and is very useful for the ASIC design of SET devices.
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