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检索条件"机构=National Laboratory for Parallel and Distributed Processing"

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Load scheduling: Reducing pressure on distributed register files for free

Load scheduling: Reducing pressure on distributed register f...

引用

Asia and South Pacific Design Automation Conference

作者： Mei Wen Nan Wu Maolin Guan Chunyuan Zhang National Laboratory for Parallel and Distributed Processing Changsha Hunan China

ISBN: (纸本)9781424419210

In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered VLIW processors with distributed register files while not increasing VLIW scheduling length. We have implemented load scheduling in compiler for Imagine and FT64 stream processors. The result shows that the proposed technique effectively reduces the number of variables spilled to memory, and can even eliminate it. The algorithm presented in this paper is extremely efficient in embedded processor with limited register resource because it can improve registers utilization instead of increasing the requirement for the number of registers.

关键词： Registers Processor scheduling VLIW Streaming media Delay Memory management Laboratories distributed processing Scheduling algorithm Power dissipation

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Weakly hard real-time scheduling algorithm for multimedia embedded system on multiprocessor platform

Weakly hard real-time scheduling algorithm for multimedia em...

引用

IEEE International Conference on Ubi-Media Computing

作者： Tong Wu Shiyao Jin NUDT Changsha Hunan National Laboratory for Parallel and Distributed Processing China

ISBN: (纸本)9781424418657

Multiprocessor architectures are becoming more attractive for embedded systems, and also for multimedia embedded systems. In multimedia embedded systems, there exist both hard real-time tasks and multimedia stream with QoS guarantee. In this context, researched on integrated schedule of both hard real-time tasks and streams are urgent affairs. This paper analyzes the shortcomings of the current approach - multimedia server, and then based on the DBP algorithm, proposes an algorithm which also considers the resource constraint. According to the different budget schemes, greedy algorithm and optimistic algorithm are brought up. Results show the performance of the algorithms.

关键词： Real time systems Scheduling algorithm Multimedia systems Embedded system Streaming media Processor scheduling Job shop scheduling Very large scale integration Computer architecture Laboratories

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DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor

DMA Performance Analysis and Multi-core Memory Optimization ...

引用

International Symposium on parallel and distributed processing with Applications, ISPA

作者： Yong Dou Lin Deng Jinhui Xu Yi Zheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China

The Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. The DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.

关键词： Performance analysis Bandwidth Delay Benchmark testing Multicore processing Data communication Context Performance evaluation Mathematical analysis Fitting

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Symbolic Model Checking APSL

Symbolic Model Checking APSL

引用

第二届IFIP/IEEE软件工程理论基础国际研讨会(TASE 2008)(Second IFIP/IEEE International Symposium on Theoretical Aspects of Software Engineering)

作者： Wanwei Liu Ji Wang Huowang Chen Xiaodong Ma National Laboratory for Parallel and Distributed Processing School of computer National University of Defense Technology China

PSL is a kind of temporal logic which uses SEREs as additional formula constructs. We present a variant of PSL, namely APSL, which replaces SEREs with finite automata. APSL and PSL are of the exactly same expressiveness. In this paper, we extend the LTL symbolic model checking algorithm to that of APSL, and present a tableau based APSL verification approach. Moreover, we show how to implement this algorithm via the BDD based symbolic approach.

关键词： Automata Logic Data structures Boolean functions Binary decision diagrams Software engineering Laboratories distributed processing Concurrent computing distributed computing

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Detecting the Sybil Attack Cooperatively in Wireless Sensor Networks

Detecting the Sybil Attack Cooperatively in Wireless Sensor ...

引用

International Conference on Computational Intelligence and Security

作者： Shaohe Lv Xiaodong Wang Xin Zhao Xingming Zhou National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424441969

Sybil attack is a network threat introduced by one or more malicious nodes to declare numerous illegal identifies to confuse or even collapse the network applications. A new detection mechanism, called CRSD, is proposed for static wireless sensor networks, which takes use of the received signal strength (RSS) to infer the distance between two identities and further determines the positions relation of the interesting identities by use of the RSS information from multiple neighbor nodes, e.g., via node cooperation. A Sybil attack is detected when two or more different identities have almost the same position. The analysis and simulation results show that, first, Sybil attack deteriorates the system performance significantly and second, CRSD can detect such attack in most cases, thus protecting the overall performance effectively.

关键词： Wireless sensor networks Computational intelligence national security Laboratories distributed processing Electronic mail Performance analysis Analytical models System performance Protection

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Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA

Fine-grained parallel application specific computing for RNA...

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Yong Dou Fei Xia Xingming Zhou Xuejun Yang National Laboratory for Parallel&Distributed Processing National University of Defense Technology ChangSha China

In the field of RNA secondary structure prediction, the Zuker algorithm is one of the most popular methods using free energy minimization. However, general-purpose computers including parallel computers or multi-core computers exhibit parallel efficiency of no more than 50% on Zuker. FPGA chips provide a new approach to accelerate the Zuker algorithm by exploiting fine-grained custom design. Zuker shows complicated data dependences, in which the dependence distance is variable, and the dependence direction is also across two dimensions. We propose a systolic array structure including one master PE and multiple slave PEs for fine grain hardware implementation on FPGA. We exploit data reuse schemes to reduce the need to load energy matrices from external memory. We also propose several methods to reduce energy table parameter size by 85%. To our knowledge, our implementation with 16 PEs is the only FPGA accelerator implementing the complete Zuker algorithm. The experimental results show a factor of 14 speedup over the ViennaRNA-1.6.5 software for 2981-residue RNA sequence running on a PC platform with Pentium 4 2.6 GHz CPU.

关键词： Computer applications Concurrent computing RNA Field programmable gate arrays Application software Prediction algorithms Minimization methods Acceleration Algorithm design and analysis Systolic arrays

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Analyzing the Efficiency and Bottleneck of Scientific Programs on Imagine Stream Processor by Simulation

Analyzing the Efficiency and Bottleneck of Scientific Progra...

引用

International Symposium on parallel and distributed processing with Applications, ISPA

作者： Yonggang Che Chuanfu Xu Zhenghua Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Imagine stream processor has shown high performance and efficiency for media applications. Its potential for scientific applications is of great interest to the high performance computing community. This paper investigates this subject from a new angle. It roughly classifies the scientific programs into three classes based on their computation to memory access ratios. For each class, typical programs are programmed with StreamC/KernelC stream language and simulated based on the cycle-accurate simulator of Imagine. In-depth analysis is carried out for the performance data, with special attentions on the performance bottlenecks. The performance data obtained on Imagine are compared against data on two general-purpose x86 processors. The results show that programs with no DRAM accesses attain high floating point performance and efficiencies on Imagine. These programs' performance is only restricted by limited ILP (Instruction-Level parallelism) and load imbalance across ALUs. Programs with computation to memory operation ratios O(n) attain absolute floating point performance on Imagine comparable to that obtained on general-purpose processors, but their floating-point efficiencies are not satisfactory. It is essential to optimize these programs for high SRF (Stream Register File) and LRF (Local Register File) reuse and high ILP on Imagine. Programs with lower computation to memory operation ratios attain much lower floating-point performance and efficiencies on Imagine, compared to those obtained on x86 processors.

关键词： Image analysis Streaming media Analytical models Computer architecture Computational modeling High performance computing Bandwidth Arithmetic Application software Scientific computing

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Automating Software FMEA via Formal Analysis of Dependence Relations

Automating Software FMEA via Formal Analysis of Dependence R...

引用

IEEE Annual International Computer Software and Applications Conference (COMPSAC)

作者： Wei Dong Ji Wang Changzhi Zhao Xian Zhang Jie Tian School of Computer National University of Defense Technology China National Laboratory for Parallel and Distributed Processing China

The paper presents the ongoing work of studying FMEA method for embedded safely critical software via formal analysis of various dependence relations among software elements, which can fairly improve the automation and precision of both system level and detailed level FMEA. These dependence relations are depicted by the formal models abstracted from software design and implementation, and the FMEA processes for both structural and object-oriented software are proposed respectively. The initial result of case study shows the effectiveness of the approach.

关键词： Software Unified modeling language Safety Aircraft Object oriented modeling Atmospheric modeling Software reliability

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An Efficient Algorithm for the Least Areas Path Problem

An Efficient Algorithm for the Least Areas Path Problem

引用

ISECS International Colloquium on Computing, Communication, Control, and Management, CCCM

作者： Gaojun Fan Shiyao Jin Ational Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China

The goal of the least areas path problem (LAPP) is to find a path traversing through a given region covered by a set of areas with any arbitrary shape, between a given pair of points and with the property that each point on the path is covered by the least areas. Different the weighted region optimal path problem, the LAPP asks for the cost of each step in path is as low as possible. Based on the relationship between boundaries of sub-regions and the least areas path, we can transform this continuous-domain problem to a discrete one by calculating the coverage of curves of sub-regionspsila boundaries. Depending on binary-search and breadth-first-search, an efficient and fast algorithm was devised for solving the LAPP.

关键词： Algorithm design and analysis Ad hoc networks Approximation algorithms Complexity theory Strontium Approximation methods Computational geometry

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Optimal Placement of Application-Level Checkpoints

Optimal Placement of Application-Level Checkpoints

引用

IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Panfeng Wang Zhiyuan Wang Yunfei Du Xuejun Yang Haifang Zhou National Laboratory for Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha Hunan China

One of the basic problems related to the efficient application-level checkpointing is the placement of checkpoints in the source codes. In this paper we discuss two common questions with a source-to-source precompiler ALEC: 1) if there are N checkpoints in the application's source code, how to pick M checkpoints out of them minimizing the total amount of checkpoint data? 2) if there are no checkpoint in the application's source code, how to insert a set of checkpoints minimizing the amount of checkpoint data? We reveal that these two questions can both be abstracted as a mathematic model which is similar to the 0-1 integer programming model, and the model can be solved using implicit enumeration method. The solving methods proposed in the paper have been implemented and integrated into ALEC. Experimental results show that the method is efficient.

关键词： Checkpointing Fault tolerance Fault tolerant systems Program processors Computers Flow graphs Data structures

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