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An adaptive data objects placement algorithm for non-uniform capacities

3rd International Conference on Grid and Cooperative Computing, GCC2004

作者： Liu, Zhong Zhou, Xing-Ming National Laboratory for Parallel and Distributed Processing Changsha410073 China

ISBN: (纸本)3540235647

The capacities of storage nodes usually are non-uniform and storage nodes are dynamically changed in large-scale distributed storage systems. In this paper, a novel dynamic data objects placement algorithm is proposed;data objects are always distributed among the storage nodes according to their capabilities. When storage nodes are changed, it affords to immediately rebalance data objects distribution according to weight of storage nodes. Simulation results indicates that data objects are always distributed among the storage nodes according to their capabilities and data objects are migrated throughout all storage nodes in parallel, resulting in minimum amount of replacement of objects. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Multiprocessing systems

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Accelerated Selective Algebraic Multigrid Method for Fully-Coupled Incompressible Flow Solver

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International Journal of Computational Fluid Dynamics 2025年

作者： Liang, Yuechao Guo, Xiao-Wei Zhang, Qingyang Li, Chao Liu, Jie Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha China College of Computer Science and Technology National University of Defense Technology Changsha China

The fully coupled pressure-based algorithm is widely recognised for its superior convergence and robustness in solving incompressible flow problems. However, the increased scale of equations and the difficulty in solving linear systems have limited the widespread use of this algorithm in large-scale simulations. This paper presents an optimised block selective algebraic multigrid method significantly reducing computational complexity. Our approach employs a parallel modified independent set algorithm, allowing each process to perform matrix coarsening individually. Furthermore, an aggressive coarsening strategy is introduced to reduce complexity and enable the solution of larger-scale problems. Numerical experiments demonstrate that the solution time is shortened by 14% to 49% compared to the latest existing methods and outperforms the segregated algorithm. By addressing the computational challenges associated with the selective algebraic multigrid solver, this work unleashes the superior convergence properties of the fully coupled method. © 2025 Informa UK Limited, trading as Taylor & Francis Group.

关键词： Convergence of numerical methods

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Two improved GPU acceleration strategies for force-directed graph layout

Two improved GPU acceleration strategies for force-directed ...

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International Conference on Computer Application and System Modeling

作者： Wang, Yong-Xian Li, Zong-Zhe Yao, Lu Cao, Wei Wang, Zheng-Hua National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424472369

Force directed approach is one of the most widely used methods in graph drawing research. However, the running time is increased intolerablely along with the enlargement of the graph size, which restricts the algorithm's practicability. By the aid of GPU (graphics processing unit) computing platform, we can speed-up the graph layout with low cost, but the existing GPU implementation mainly employees an "one-by-one" style to update the vertex' coordination per iteration, which has a lower convergent rate than the "batch" style which is instead used commonly in traditional CPU implementation. As a result, the aesthetics of graph layout would be decreased if the total running time is restricted. It is hard to achieve both a high speedup factor of GPU over CPU and a high convergent rate in existing GPU computing implementation. In order to solve this problem partially, this paper presents two new strategies to implement the large-scale graph layout on CPU+GPU heteromerous platform to accelerate the force directed layout for graph drawing problem. The numerical computation results show that our GPU implementation can dramatically improve the performance of force-direct layout and is 20 times on a NVIDIA GeForce 9800 GT GPU at 1.44 GHz faster than the one on single-CPU core of Intel Pentium 4 PC at 3.0 GHz for the graph layout with moderate size (typically 1000 vertices). © 2010 IEEE.

关键词： Graphics processing unit

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A exploratory study of @-mention in GitHub's Pull-requests 21

A exploratory study of @-mention in GitHub's Pull-requests

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21st Asia-Pacific Software Engineering Conference, APSEC 2014

作者： Zhang, Yang Yin, Gang Yu, Yue Wang, Huaimin National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha410073 China

ISBN: (纸本)9781479974252

Pull-request mechanism is an outstanding social development method in GitHub. @-mention is a social media tool that deeply integrated with pull-request mechanism. Recently, many research results show that social media tools can promote the collaborative software development, but few work focuses on the impacts of @-mention. In this paper, we conduct an exploratory study of @-mention in pull-request based software development, including its current situation and benefits. We obtain some interesting findings which indicate that @-mention is beneficial to the processing of pull-request. Our work also proposes some possible research directions and problems of the @-mention. It helps the developers and researchers notice the significance of @-mention in the pull-request based software development. © 2014 IEEE.

关键词： Software design

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Implementation of a Fine-Grained parallel full pipeline Schnorr–Euchner sphere decoder algorithm accelerator on Field-Programmable gate array 4th

Implementation of a Fine-Grained parallel full pipeline Schn...

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4th International Conference on Computer Engineering and Networks, CENet2014

作者： Li, Shijie Guo, Lei Dou, Yong Jiang, Jingfei National laboratory for parallel and distributed processing National University of Defense Technology Changsha410073 China

ISBN: (纸本)9783319111032

A new parallel full pipeline accelerator implemented on fieldprogrammable gate array (FPGA) for the Schnorr–Euchner sphere decoding (SE– SD) algorithm is presented in this paper. We firstly transform the serial SE–SD algorithm into a parallel one. Afterwards, we use multiple processing elements (PEs) to deal with the workload (particularly for tree searching in the SE–SD algorithm) in parallel. Each separated SE–SD search workload is divided averagely. Each PE searches a sub-tree by using a multilevel pipeline to increase the data throughput, and the whole system obtains a batch of different input data chronologically. We select the number of PEs to distribute our system according to the hardware platform by using a distribution unit. We’ve successfully placed four PEs in an accelerator and eight accelerators in a single FPGA (XC6VLX240T). The system obtains remarkable benefit in changing the accelerate mode, including latency- and throughput-prior modes. © Springer International Publishing Switzerland 2015.

关键词： MIMO systems

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An efficient load balancing method for constant degree P2P systems

An efficient load balancing method for constant degree P2P s...

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2010 International Conference on Computer Design and Applications, ICCDA 2010

作者： Wang, XiaoHai Peng, YuXing Li, DongSheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781424471638

Constant degree P2P systems are turning into the P2P domain's promising hotspot due to their good properties. However, it is often hard to convert a standard constant degree digraph to a flexible DHT schema adapting to dynamic P2P environments. Thus, most research about constant degree P2P focus on DHT's construction and maintenance, while leaving optimization and supporting to upper-layer application behind, such as complex query, load balance, etc. Combining constant degree topology's bit-shift routing schema, we presents an efficient load balancing algorithm based on Reverse Spanning Tree (REST) for constant degree P2P systems. Using the statistic information in joining process, REST judges how many Virtual Servers that a new join super peer can run, and then join all virtual servers evenly and fast with low cost based on the Spanning Tree Peer Set. Experimental results show, without additional data structure, REST keeps the constant degree P2P system load-balanced by assuring each peer of owning a key space proportional to its capability. © 2010 IEEE.

关键词： Trees (mathematics)

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Approximating quantified SMT-solving with SAT

Approximating quantified SMT-solving with SAT

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International Conference on Secure Software Integration and Reliability Improvement Companion

作者： Fu, Xianjin Liu, Wanwei Li, Jing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769544540

Satisfiability Modulo Theories (SMT) is an extension of SAT towards FOL. SMT solvers have proven highly scalable and efficient for problems based on some ground theorems. However, SMT problems involving quantifiers and combination of theorems is a long-standing challenge, which has been a major bottleneck of practical application of SMT solvers in some fields. We reveal a decidable fragment of FOL involving quantifiers, which could not be solved by SMT solvers such as Z3, CVC3, etc., and show how to convert them into model checking problems. © 2011 IEEE.

关键词： Model checking

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Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA

Fine-grained parallel application specific computing for RNA...

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Embedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09

作者： Dou, Yong Xia, Fei Jiang, Jingfei National Laboratory for Parallel and Distributed Processing National University of Defence Technology 410073 ChangSha China

ISBN: (纸本)9781605586267

In the field of RNA secondary structure prediction, the CYK (Coche-Younger-Kasami) algorithm is a most popular methods using SCFG (stochastic context-free grammars) model. However, general purpose parallel computers including SMP multiprocessors or cluster systems exhibit low parallel efficiency and they are too expensive to be used easily for many research institutes. FPGA chips provide a new approach to accelerate the CYK algorithm by exploiting fine-grained custom design. The CYK algorithm shows complicated data dependence, in which the dependence distance is variable, and the dependence direction is also across two dimensions. We propose a systolic array structure including one master PE and multiple slave PEs for fine grain hardware implementation on FPGA. We partition tasks by columns and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load matrix from external memory. To our knowledge, our implementation with 16 PEs is the only FPGA accelerator implementing the complete CYK/inside algorithm. The experimental results show a factor of more than 14 speedup over the Infernal-0.55 software running on a PC platform with Pentium 4 2.66GHz CPU. The computational power of our platform with FPGA accelerator is comparable to a PC cluster consisting of 20 Intel-Xeon CPUs for RNA secondary structure prediction using SCFGs, but the hardware cost and power consumption is only about 15% and 10% of the latter respectively. Copyright 2009 ACM.

关键词： Field programmable gate arrays (FPGA)

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Labeled topic detection of open source software from mining mass textual project profiles

Labeled topic detection of open source software from mining ...

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1st International Workshop on Software Mining, SoftwareMining-2012 - Held in Conjunction with the 18th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, KDD-2012

作者： Wang, Tao Yin, Gang Li, Xiang Wang, Huaimin National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781450315609

Nowadays open source software has become an indispensable basis for both individual and industrial software engineering. Various kinds of labeling mechanisms like categories and tags are used in open source communities to annotate projects and facilitate the discovery of certain software However as large amounts of software are attached with no/few labels or the existing labels are from different ontology space, it is still hard to retrieve potentially topic-relevant software. This paper highlights the valuable semantic information of project descriptions and labels, proposes labeled software topic detection LSTD a hybrid approach combining topic models and ranking mechanisms to detect and enrich the topics of software by mining the large amount of textual software profiles, which can be employed to do software categorization and tag recommendation. LSTD makes use of labeled LDA to capture the semantic correlations between labels and descriptions and then construct the label-based topic-word matrix. Based on the generated matrix and the generality of labels, LSTD designs a simple yet eficient algorithm to detect the latent topics of software that expressed as relevant and popular labels. Comprehensive evaluations are conducted on the large-scale datasets of representative open source communities and the results validate the effectiveness of LSTD.

关键词： Open source software

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Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA

Special-purposed VLIW architecture for IEEE-754 quadruple pr...

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29th IEEE International Conference on Computer Design 2011, ICCD 2011

作者： Lei, Yuanwu Dou, Yong Shen, Li Zhou, Jie Guo, Song National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781457719523

This work explores the feasibility to implement IEEE-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. Then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). The proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. The performance is improved through the explicitly parallel technology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. The experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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