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A Case Study of SWIM: Optimization of Memory Intensive Application on GPGPU

A Case Study of SWIM: Optimization of Memory Intensive Appli...

引用

International Symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Wei Yi Yuhua Tang Guibin Wang Xudong Fang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Recently, GPGPU has been adopted well in the High Performance Computing (HPC) field. The limited global memory bandwidth poses a great challenge to many GPGPU programmers trying to exploit parallelism within the CPU-GPU heterogeneous platform. In this paper, we choose SWIM, a typical memory intensive application from the SPEC OMP 2001 benchmark suite, for case study. We attempt to optimize the performance and energy consumption of the application utilizing different memory access mechanisms and present optimization methods including matrix transposition and kernel fusion. The experimental results on the Intel Core TM i920 CPU plus GeForce GTX 295 platform shows that, the proposed optimizing methods achieve a speedup of 8.7X over the original OpenMP program and reduce the energy consumption by 83% for the problem size of 2048*2048.

关键词： Instruction sets Kernel Bandwidth Graphics processing unit Memory management Energy consumption Central processing Unit

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Error Detection by Redundant Transaction in Transactional Memory System

Error Detection by Redundant Transaction in Transactional Me...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Wei Song Jia Jia Yu-xing Peng National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

This paper addresses the issue of error detection in transactional memory, and proposes a new method of error detection based on redundant transaction (EDRT). This method creates a transaction copy for every transaction, and executes both original transactions and transaction copies on adequate processor cores, and achieves error detection by comparing the execution results. EDRT utilizes the data-versioning mechanism of transactional memory to achieve the acquisition of an approximate minimum error detection comparing data set, and the acquisition is transparent and online. At last, this paper validates the EDRT through 5 test programs, including 4 SPLASH-2 benchmarks. The experimental results show that, the average error detecting cost is about 3.68% relative to the whole program, and it's only about 12.07% relative to the transaction parts of the program.

关键词： Instruction sets Fault tolerant systems Hardware computer architecture Redundancy

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Optimizing Adaptive Synchronization in parallel Simulators for Large-scale parallel Systems and Applications

Optimizing Adaptive Synchronization in Parallel Simulators f...

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International Conference on computer and Information Technology (CIT)

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

This paper addresses the optimization of parallel simulators for large-scale parallel systems and applications. Such simulators are often based on parallel discrete event simulation with conservative or optimistic protocols to synchronize the simulating processes. The paper considers how available future information about events and application behaviors can be efficiently extracted and further exploited to improve the performance of adaptive optimistic protocols. First, we extract information about future events and their dependencies in application traces to guide adaptive adjustments of time window in trace-driven parallel simulation. Second, we use information about application behaviors, specifically the iterative behavior found in many applications, to avoid the unnecessary adjustments of time window. These techniques are implemented in the BigSim simulator and tested by real-world and standard benchmark applications including Jacobi3D and HPL. The results show that our optimization approaches can reduce the execution times of simulation ranging from 11% up to 32%. Moreover, our methods are easy to implement and don't need to augment compilers or even modify the core codes of parallel simulators.

关键词： Adaptation model Computational modeling Schedules Optimization Protocols Synchronization Analytical models

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Towards Online Application Cache Behaviors Identification in CMPs

Towards Online Application Cache Behaviors Identification in...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Xiaomin Jia Jiang Jiang Tianlei Zhao Shubo Qi Minxuan Zhang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

On chip multiprocessors (CMPs) platforms, multiple co-scheduled applications can severely degrade performance and quality of service (QoS) when they contend for last-level cache (LLC) resources. Whether an application will impose destructive interference on co-scheduled applications is largely dependent on its own inherent cache access behavior characteristics. In this work, we first present case studies that show how inter-application interferences result in undesirable performance in both shared and private cache based LLC designs. We then propose a new online approach for application cache behavior identification on the basis of detailed simulation and analysis with SPEC CPU2006 benchmarks. We demonstrate that our approach can more concisely identify application cache behaviors. Moreover, the proposed approach can be implemented directly in hardware to dynamically identify the application cache behaviors at runtime. Finally, we show with two case studies that how the proposed approach can be adopted by both shared and private based cache sharing mechanisms, i.e. cache partitioning algorithms (CPAs) and cache spilling techniques, for more concise cache resource management.

关键词： Benchmark testing Measurement Throughput Servers Interference Aerospace electronics Heuristic algorithms

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Chameleon: Adaptive energy-efficient heterogeneous network-on-chip

Chameleon: Adaptive energy-efficient heterogeneous network-o...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Ji Wu Dezun Dong Xiangke Liao Li Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Multi-NoC (multiple network-on-chip) has demonstrated its advantages in power gating for reducing leakage power. This work presents Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a performance-aware traffic allocation policy, Chameleon is able to achieve both high power efficiency and good performance at varying network utilization. Our experimental results show that Chameleon delivers an average of 3.39% higher performance than Catnap, the best in the literature. More importantly, Chameleon consumes an average of 17.16% less power than Catnap.

关键词： Resource management Routing Algorithm design and analysis Optimization Logic gates computers Power demand

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TRUSTIE: Design of a Trustworthy Software Production Environment

TRUSTIE: Design of a Trustworthy Software Production Environ...

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IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Huaimin Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Internet fundamentally changes the model of software development, the demands of software quality, and the process of software resource sharing. Internet- based environment for trustworthy software production is recognized as a key topic of software engineering in both academic and software industry. In this paper, the concepts and models of trustworthy software are introduced which dominate the design of Trustie environment. Trustie provides trustworthy software components sharing by an evolving software repository, and provides collaborative software development in a customizable development platform powered by a software production line framework. Finally the layered practices of research and application based on Trustie preliminarily demonstrate the effectiveness as well as the promising future of this environment.

关键词： Software Production Collaboration Internet Resource management Software engineering Programming

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Simulation and analysis of single-electron transistors with 1-dimension multiple islands

Simulation and analysis of single-electron transistors with ...

引用

IEEE Conference on Nanotechnology

作者： Bingcai Sui Yaqing Chi Hailiang Zhou Chao Zhang Liang Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

ISBN: (纸本)9781424448326

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. Based on the Monte Carlo (MC) and stable diagram method, the critical problems during simulating and analyzing the SETs with multi-islands are investigated, e.g. capacitance matrix, potential of the islands, the free energy and so on. Meanwhile, double-island SET is simulated and analyzed as an example of SETs with 1-D muti-islands in detail. For the first time, 3-D stable diagram is obtained, and some new phenomena are analyzed in the paper. And through analyzing the result it's shown that although SETs with 1-D muti-islands is more useful and powerful than SETs with single island, there inevitably exists many effects because of the coupling energy between the islands.

关键词： Analytical models Single electron transistors Tunneling Carbon nanotubes Capacitance Voltage Energy consumption Capacitors Very large scale integration Temperature

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Invalid Pointer Dereferences Detection for CPS Software Based on Extended Pointer Structures

Invalid Pointer Dereferences Detection for CPS Software Base...

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International Conference on Secure Software Integration and Reliability Improvement Companion (SSIRI-C)

作者： Longming Dong Wei Dong Liqian Chen National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Invalid pointer dereferences, such as null pointer dereferences, dangling pointer dereferences and double frees, are a prevalent source of software bugs in CPS software, due to flexible dereferencing pointers along various pointer fields. Existing tools have high overhead or are incomplete, thereby limiting their efficiency in checking the kind of CPS software with shared and mutable memory. In this paper, we present a novel extended pointer structure for detecting all invalid pointer dereferences in this kind of CPS software. We propose an invalid pointer dereferences detection algorithm based on the uniform transformation of abstract heap states. Experimental evaluation about a set of large C benchmark programs shows that the proposed approach is sufficiently efficient in detecting invalid pointer dereferences of CPS software with shared and mutable memory.

关键词： Abstracts Software Frequency modulation Semantics Switches Detection algorithms Runtime

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Optimizing Depthwise Convolutions on ARMv8 Architecture 23rd

Optimizing Depthwise Convolutions on ARMv8 Architecture

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23rd International Conference on parallel and distributed Computing, Applications, and Technologies, PDCAT 2022

作者： Hao, Ruochen Wang, Qinglin Yin, Shangfei Zhou, Tianyang Zhang, Qingyang Mei, Songzhu Shen, Siqi Liu, Jie Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China College of Computer National University of Defense Technology Changsha410073 China Xiamen University Xiamen China

ISBN: (纸本)9783031299261

Depthwise convolutions are widely used in lightweight convolutional neural networks (CNNs). The performance of depthwise convolutions is mainly bounded by the memory access rather than the arithmetic operations for classic convolutions so that direct algorithms are often more efficient than indirect ones (matrix multiplication-, Winograd-, and FFT-based convolutions) with additional memory accesses. However, the existing direct implementations of depthwise convolutions on ARMv8 architectures feature a bad trade-off between register-level reuse of different tensors, which usually leads to sub-optimal performance. In this paper, we propose a new direct implementation of depthwise convolutions by means of implicit padding, register tiling, etc. Compared to the existing ones, our new implementations can incur much less communication overhead between registers and cache. Experimental results on two ARMv8 CPUs show that our implementation can averagely deliver 4.88 × performance improvement over the existing direct ones in open-source libraries. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Convolution

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Effect of self and cross-coupling capacitance on stability diagram in a metallic double-dot device

Effect of self and cross-coupling capacitance on stability d...

引用

International Conference on Nanoscience and Nanotechnology, ICONN

作者： Bingcai Sui Liang Fang Yaqing Chi National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

We investigate the effect of self and cross-coupling capacitance on stability diagram in a metallic double-dot device by theory and method. In linear transport regime, cross-coupling capacitances affect the dimension of the honeycomb cell and the distance of two triple points, while self capacitances only slightly broaden the boundary of the cell and make two triple point closer. In nonlinear transport regime, cross-coupling capacitances stretch the current region and charge region in the mid-line direction, while self capacitances extend the region of current regions but not change the shape of the stability cells. Cross-coupling capacitances make stronger impact on the dimensions of stability diagram than self capacitance. But the self-capacitance must be included in the current calculation if its value can not be neglected with respect to the device parameters.

关键词： Stability analysis Tunneling Couplings Quantum capacitance Shape Junctions

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