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Power analysis and optimizations for GPU architecture using a power simulator

Power analysis and optimizations for GPU architecture using ...

引用

2010 3rd International Conference on Advanced computer Theory and Engineering, ICACTE 2010

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465408

As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus on the power analysis and optimizations for GPU architecture. The main contributions of this paper are: firstly, we establish a GPU power reserach platform, which is extended from an existing GPU simulator with several power models;secondly, we validate that, as the gap between shader core and memory speed becomes larger and larger, integrating more shader cores or enhancing running frequencies may not bring better performance, but results in higher energy consumption;thirdly, we show that traditional power optimization methods for CPUs, such as dynamic frequency scaling and concurrencythrottling, could be effectively applied on GPU architectures for better power efficiency, especially for memory-intensive applications. © 2010 IEEE.

关键词： Simulators

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Sim-spm: A simplescalar-based simulator for multi-level SPM memory hierarchy architecture

Sim-spm: A simplescalar-based simulator for multi-level SPM ...

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IEEE International Conference on High Performance Computing and Communication

作者： Ren, Xiaoguang Tang, Yuhua Tang, Tao Ye, Sen Wang, Huiquan Zhou, Jing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9780769542140

As a fast on-chip SRAM managed by software (the application and/or compiler), Scratchpad Memory (SPM) is widely used in many fields. This paper presents a SimpleScalar-based multi-level SPM memory hierarchy architecture simulator Sim-spm. We simulate the hardware of the multi-level SPM memory hierarchy successfully by extending Sim-outorder, which is an out-of-order simulator from SimpleScalar. Through the simulating memory method, the simulation framework of the multi-level SPM memory hierarchy has been built under the existing ISA (Instruction Set Architecture), which largely reduces the requirement to modify the existing compiler. The experimental results show that Sim-spm can accurately simulate the running state of the processor with a multi-level SPM memory hierarchy architecture, and it has a good prospect for the research of multi-level SPM memory hierarchy architecture. © 2010 IEEE.

关键词： Simulators

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Media access control protocol based on hybrid antennas in ad hoc networks

Media access control protocol based on hybrid antennas in ad...

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International Conference on Autonomic and Trusted Computing

作者： Ding, Yanrong Wang, Xiaodong Shen, Hu Guo, Pengyu National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769542720

Nested Circular Directional MAC, a modified medium access control protocol of DMAC protocol, is proposed in this paper to support both directional antennas and omni-directional antennas simultaneously in one Ad Hoc network. Omni-directional antennas follow the RTS/CTS mechanism which is multi-hop and directional antennas follow the DRTS/DCTS mechanism, ensuring the asymmetric communication effectively. In order to resolve new deafness problem and hidden terminal problem, the directional antennas also use circular DRTS and nested antenna circumrotation. Simulation results show that NCDMAC supports hybrid antennas effectively and is better than MMAC and Circular-MAC in terms of increasing throughput, but it also increases the communication delay. © 2010 IEEE.

关键词： Ad hoc networks

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Metal interference analysis and design rules of on chip antennas for wireless interconnect

Metal interference analysis and design rules of on chip ante...

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International Symposium on Signals, Systems and Electronics

作者： He, Xiaowei Zhang, Minxuan Li, Jinwen Li, Shaoqing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9781424463558

The influence of on-chip metal interconnections, power grids, heat sink together with packaging, and metal dummy fills on the transmission characteristics of a 2mm-long integrated dipole antenna pair has been investigated in this paper. These metal structures and placements have been classified and particular simulations are performed to explore the interference effects of neighboring various metal structures on transmission gain, phase, impedance and radiation pattern for on-chip dipole antenna pair. By virtue of the experimental results and analyses, several experiential linear expressions for antenna pair gain and phase in interference circumstances are obtained using numerical fit. A set of design rules is concluded accordingly for guiding on-chip antenna layout and design targeting wireless interconnect. © 2010 IEEE.

关键词： Dipole antennas

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nSET: Novel Simulation Method for Single-Electron Tunnel Device with 1-Dimension Multiple Islands

nSET: Novel Simulation Method for Single-Electron Tunnel Dev...

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3rd IEEE International NanoElectronics Conference (INEC)/Symposium on Nanoscience and Nanotechnology in China

作者： Sui, Bingcai Chi, Yaqing Fang, Liang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan 410073 China National University of Defense Technology China

ISBN: (纸本)9781424435432

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. A new simulation method-nSET, is introduced in this paper Compared with other methods, nSET can simulate the SET device with 1-Dimension multiple islands with high speed and accuracy. Through the comparison, it can be get that nSET is accurate and fast compared with the classical Monte Carlo(MC) simulator, and is very useful for the ASIC design of SET devices.

关键词： Monte Carlo simulation single-electron tunneling device single-electron transistor multiple islands

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RETRACTED ARTICLE: parallel block multigrid preconditioner for 3D navier-stokes equations on unstructured grids

RETRACTED ARTICLE: Parallel block multigrid preconditioner f...

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作者： Li, Zongzhe Lu, Yao Cao, Wei Wang, Yongxian Wang, Zhenghua Parallel and Distributed Processing for National Laboratory School of Computer Science National University of Defence Lechnology Changsha Hunan 410073 China

ISBN: (纸本)9781424472369

In this paper, we explore a parallel block multigrid preconditioner based on factorization of the coefficient matrix generated in three-dimensional unstructured grids system. This preconditioner is robust with respect to the magnitude of the mesh size and the coefficient complexity, apply smoothed aggregation algebraic multigrid which using block lower-upper symmetric Gauss-Seidel(BLU-SGS) as smoother to accelerate convergent rate. We focus on this method to three-dimensional, unstructured, large-scale, parallel and NS equations' steady-state simulations. The numerical results which conducted on NACA0012 airfoil indicate that nearly optimal convergence rates and computational complexity for parallel solutions, this method also provide high speedup and efficiency for a series of processors. © 2010 IEEE.

关键词： Navier Stokes equations

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Stigmergic collaboration: A sign-based perspective of stigmergy

Stigmergic collaboration: A sign-based perspective of stigme...

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2010 International Conference on Intelligent Computation Technology and Automation, ICICTA 2010

作者： Ren, Chuanjun Huang, Hongbing Jin, Shiyao National Laboratory for Parallel and Distributed Processing College of Computer Science National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769540771

Insects build architecturally complex nests and search for remote food by collaboration work despite their limited sensors, minimal individual intelligence and the lack of a central control system. Insets' collaborations emerge as a response of the individual insects to Stigmergy. A sign-based model of Stigmergy to discuss collaboration is proposed in this paper where we picked up "sign" as a key notion to understand it. Therefore, sign is the link of all the components in a Stigmergic complex adaptive system. Based on this understanding, we propose a definition that reveals the nature of signs and exploit the significations and relationships carried by the notion of sign. Then, a sign-based model of Stigmergy is consequently reached, which captures the essentials of Stigmergy. A basic architecture of Stigmergy as well as its constituents are presented and discussed. At last, some applications of the model are discussed. © 2010 Crown Copyright.

关键词： CAS Collaboration Emergence Sign Stigmergy Emergence Volatile Oils Insecta central control system

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Implementation of encrypted data for outsourced database

Implementation of encrypted data for outsourced database

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2010 2nd International Conference on Computational Intelligence and Natural Computing, CINC 2010

作者： Wang, Zheng-Fei Tang, Ai-Guo Department of Computer Hunan Business College Changsha 410205 China National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781424477036

Encryption technology has become an important mechanism of securing data stored in the outsourced database. However, it is a difficulty to query efficiently the encrypted data and many researchers take it into consideration. To solve the problem, an encrypted schema, based on the Postgresql DBMS, is proposed Through the security dictionary and the extended SQL, the approach implements the encrypted storage and efficiently query over the encrypted data in the outsourced databases. Results of experiments validate the efficiency and feasibility of our approach. ©2010 IEEE.

关键词： Cryptography

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A high efficient in-place transposition scheme for multidimensional arrays

A high efficient in-place transposition scheme for multidime...

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3rd International Conference on Information and Computing, ICIC 2010

作者： Yuan, Jie Wu, Jian-Ping Wang, Zheng-Hua National Lab. of Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer Science National University of Defense Changsha China

ISBN: (纸本)9780769540474

This paper presents a in-place cycle-reducing method for multidimensional arrays transposition in local memory to reduce the memory R/W operations. The resulting method can significantly reduce the number of subcycles (also called following-cycles) and that of memory operations for square arrays. Taking square array 256 by 256 for example, the number of subcycles used by current available best algorithm can be reduced from 32894 to only 574, using our new method, and the memory operation number can be reduced by about 32.58%, from 98430 to 66366. Taking advantage of this new method, the elapsed time can be reduced as a result. The number of cycles and operations can also be reduced for 2D rectangle arrays with 2m rows and 2n column stored in column-major, especially n=2m, even though the improvement is not as significant as that for square arrays. The improved 2D in-place algorithm has been extended to 3D arrays, and some theoretic and numerical results are also provided. Furthermore, we develop a new in-place 3D arrays transposition algorithm. This algorithm is very important for a deep research for multidimensional arrays. Experimental results show that our algorithm can improve efficiency significantly, compared to some other 3D array transposition schemes. © 2010 IEEE.

关键词： Multidimensional array Memory operation Cycle-reducing Transposition In-place transposition Transposition arrays three-dimensional array Local Memory MULTIDIMENSIONAL

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parallel transposing and communication strategies for FFT on cluster of SMP architectures with multicore processors

Parallel transposing and communication strategies for FFT on...

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Congress on Image and Signal processing, CISP

ISBN: (纸本)9781424465149

This paper presents a high performance parallel formulation for 1-D FFT based on transpose algorithm. The parallel scheme of FFT trades off some efficiency for a more consistent level of parallel performance. It involves matrix transposition, and a new in-place transposing algorithm is introduced into the parallel matrix transposition to improve the efficiency. Depending on the size of the input n, the number of processes p, and the memory or network bandwidth, this method can achieve better parallel performance than the other on cluster of SMP architectures. Test shows us that our scheme can achieve a good speedup. ©2010 IEEE.

关键词： Fast Fourier transforms

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