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Journal of Software 2009年第3期4卷 240-246页

作者： Lu, Pingjing Che, Yonggang Wang, Zhenghua National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

The performance gap for high performance applications has been widening over time. High level program transformations are critical to improve applications' performance, many of which concern the determination of optimal values for transformation parameters, such as loop unrolling and blocking. Static approaches achieve these values based on analytical models that are hard to achieve because of increasing architecture complexity and code structures. Recent iterative compilation approaches achieve it by executing different versions of the program on actual platforms and select the one that renders best performance, outperforming static compilation approaches significantly. But the expensive compilation cost has limited their application scope to embedded applications and a small group of math kernels. This paper proposes a combinative approach--Combining Model and Iterative Compilation for Program Performance Optimization (CMIC). Such an approach first constructs a program optimization transformation model based on hardware performance counters to decide how and when to apply transformations, and then selects the optimal transformation parameters using Nelder-Mead simplex algorithm. Experimental results show that our approach can effectively improve programs' floating-point performance, reducing programs' runtime, therefore, lessening the performance gap for high-performance applications. © 2009 ACADEMY PUBLISHER.

关键词： Digital arithmetic

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Providing Responsiveness Requirement Based Consistency in DVE

Providing Responsiveness Requirement Based Consistency in DV...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Wei Zhang Hangjun Zhou Yuxing Peng Sikun Li National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China

Consistency and responsiveness are two important factors in providing the sense of reality in distributed Virtual Environment (DVE). However, it is not easy to optimize both aspects because of the trade-off between these two factors. As a result, most existing consistency maintenance methods ignored the responsiveness requirements, or just assumed a simple responsiveness requirement model which cannot meet the real need of DVE systems. In this paper, we first present a new responsiveness requirement model. The model can describe requirement satisfaction situation of each node. Base on this model, we propose a responsiveness requirement based consistency method. The method can adjust the utilization of time resource according to the requirements of different nodes and improve the overall responsiveness performance by at least 20%. Therefore, it provides a good support to increase the applicability of DVE systems.

关键词： Delay effects Virtual environment distributed processing computer science Games Distance learning Electronic commerce Safety Research and development Real time systems

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Anode-ALM: An Aggregation-Based Application Level Multicast for Media Streaming

Anode-ALM: An Aggregation-Based Application Level Multicast ...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Feng Liu Yuxing Peng Xicheng Lu Parallel and Distributed Processing Laboratory School of Computer Science and Technology National University of Defense Technology Changsha China

Building application level multicast (ALM) for media streaming, we had better keep the invariability of source to-end delay (S2EDelay) of any node on the tree, so as to avoid delay jitter problem. In this paper, we proposed an aggregation-based ALM architecture, which aggregates the unstable nodes within a local area into a relative stable aggregation node Anode, and then builds tree by Anodes. Anode shields node's dynamicity inside and behaves as a stable one outside. To build the architecture, we first proposed an Anode structure by n-dimension anti-cube, and proposed a distributed algorithm to bind the logic view and physical view of an Anode dynamically by the differentiation and assimilation operations, which maintain the integrality of the logic view while the physical view changes dynamically. Experiment results indicate that our algorithm can keep the S2EDelay invariability of the built ALM tree effectively.

关键词： Streaming media Anodes Delay Stability Application software Jitter distributed algorithms Logic Internet Network topology

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A Two-Phase Mapping Method for parallel Applications Simulation

A Two-Phase Mapping Method for Parallel Applications Simulat...

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International Conference on Computational Intelligence and Software Engineering (CiSE)

作者： Jianbin Fang Chuanfu Xu Yonggang Che Yufen Weng Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Efficient mapping of logical processes to physical processes is one of key technologies to accelerate parallel performance simulation. Aiming at minimizing the communications between SMP nodes and between host physical processes, this paper presents a novel method named TPsmp-LP 3 M. It automatically extracts communication pattern of logical processes from trace and then generates a two-phase mapping from logical processes to SMP clusters. Experimental results show that TPsmp-LP 3 M can outperform the regular mapping method by up to 20.2%.

关键词： Computational modeling computer simulation Bandwidth Predictive models Discrete event simulation Concurrent computing parallel processing Application software Laboratories distributed processing

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iRank: Supporting Proximity Ranking for Peer-to-Peer Applications

iRank: Supporting Proximity Ranking for Peer-to-Peer Applica...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Yongquan Fu Yijie Wang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology China

Proximity ranking according to end-to-end network distances (e.g., Round-Trip Time, RTT) can reveal detailed proximity information, which is important in network management and performance diagnosis in distributed systems. However, to the best of our knowledge, there has been no similar work on this subject in the P2P computing field. We present a distributed rating method iRank, that enables proximity rankings by providing discrete ratings in a distributed manner. It formulates the proximity ranking as a rating problem that faithfully captures the proximity based on noisy distance measurements scalably and practically. The primary challenge in inferring proximity rankings is enforcing distributed ratings with complex rating policies. Our solution is based on reconstructing ratings by decomposing a centralized rating method Maximum Margin Matrix Factorization (MMMF) into independent sub-problems, that can be efficiently solved in a decentralized manner. By relaxing the dependence on infrastructure nodes that are a single point of failure and limit scalability, iRank can gracefully handle network churns. Through real network latency data sets, we demonstrate that iRank can predict ratings with low distortion, which are smaller than 20 percentage worse than the centralized method, in the context of synthetic complex rating policies.

关键词： Peer to peer computing distributed computing computer networks Network servers Application software Laboratories distributed processing Concurrent computing computer network management Conference management

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Towards efficient mapping in large-scale trace-driven parallel performance simulation

Towards efficient mapping in large-scale trace-driven parall...

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IEEE Youth Conference on Information, Computing and Telecommunication, YC-ICT

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

In parallel performance simulation of parallel systems, a large amount of logic processes (LP) must be mapped to relatively small number of physical elements (PE). Previous researches have shown that different mapping schemes could result in significant variation in the whole parallel simulation cost. In this paper, we propose, implement, and evaluate a minimum communication-guided mapping (MiniCoM) scheme for large-scale trace-driven parallel performance simulation. Guided by extracted information about interactions among LPs from previously generated traces, MiniCoM can map some most frequently interacted LPs to the same PE while trying to keep load balance between PEs. The mapping aims to minimize realistic communications among PEs which may run on different nodes of host systems with large inter-node latency. We use BigSim simulator and two target programs to evaluate MiniCoM. Our results show that MiniCoM is more efficient than blocked mapping adopted by BigSim: it can reduce the total parallel simulation runtime by up to 49%.

关键词： Large-scale systems Computational modeling parallel processing Discrete event simulation computer simulation Concurrent computing Data mining Laboratories distributed processing distributed computing

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Simulation and analysis of single-electron transistors with 1-dimension multiple islands

Simulation and analysis of single-electron transistors with ...

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IEEE Conference on Nanotechnology

作者： Bingcai Sui Yaqing Chi Hailiang Zhou Chao Zhang Liang Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

ISBN: (纸本)9781424448326

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. Based on the Monte Carlo (MC) and stable diagram method, the critical problems during simulating and analyzing the SETs with multi-islands are investigated, e.g. capacitance matrix, potential of the islands, the free energy and so on. Meanwhile, double-island SET is simulated and analyzed as an example of SETs with 1-D muti-islands in detail. For the first time, 3-D stable diagram is obtained, and some new phenomena are analyzed in the paper. And through analyzing the result it's shown that although SETs with 1-D muti-islands is more useful and powerful than SETs with single island, there inevitably exists many effects because of the coupling energy between the islands.

关键词： Analytical models Single electron transistors Tunneling Carbon nanotubes Capacitance Voltage Energy consumption Capacitors Very large scale integration Temperature

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HyperSpring: Accurate and Stable Latency Estimation in the Hyperbolic Space

HyperSpring: Accurate and Stable Latency Estimation in the H...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Yongquan Fu Yijie Wang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology China

Predicting network latencies between Internet hosts can efficiently support large-scale Internet applications, e.g., file sharing service and the overlay construction. Several study use the hyperbolic space to model the Internet dense-core and many-tendril structure. However, existing hyperbolic space based embedding approaches are not designed for accurate latency estimation in the distributed context. We present HyperSpring, which estimates latency by modelling a mass spring system in the hyperbolic similar with Vivaldi. HyperSpring adopts coordinate initialization to speed up the convergence of coordinate computation, uses multiple-round symmetric updates to escape from bad local minima, and stabilizes coordinates by compensating RTT measurements to reduce the coordinate drifts. Evaluation results based on a network trace of 226 PlanetLab nodes indicate that, compared to Euclidean-space based Vivaldi, hyperspring provides performance improvements for most nodes, and incurs slightly higher distortions for a small number of nodes.

关键词： Delay IP networks Web and internet services Large-scale systems Peer to peer computing Springs Convergence Coordinate measuring machines Distortion measurement Extraterrestrial measurements

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Matrix Inversion on the Cell/B.E. Processor

Matrix Inversion on the Cell/B.E. Processor

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Shodai Yokoyama Kazuya Matsumoto Stanislav Sedukhin Distributed Parallel Processing Laboratory Graduate School of Computer Science and Engineering University of Aizu Japan

The problem of inverting matrices is one that occurs in some problems of practical importance. This paper introduces and evaluates the block algorithm for high performance matrix inversion on the Cell Broadband Engine (Cell/B.E.) processor. The Cell/B.E. is a heterogeneous multi-core processor on a single-chip jointly developed by Sony, Toshiba and IBM, which has a very high speed of the single precision floating-point arithmetic. The discussed matrix inversion algorithm is a combination of the block algebraic path problem algorithm and the well-known block matrix inversion algorithm based on the LU decomposition. For relatively big matrices, this combined block algorithm spends the most time in computing matrix-matrix multiplication of blocks and achieves 149.4 Gflop/s on Cell/B.E., when PPE and six SPEs of PlayStation3 are used, or 93.4% of the aggregated double (PPE) and single (SPEs) precision peak performance, which is 160.0 Gflop/s.

关键词： Matrix decomposition Partitioning algorithms Floating-point arithmetic Engines Multicore processing Microprocessors Reduced instruction set computing High performance computing parallel processing computer science

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Optimization techniques of on-chip memory system based on UltraSPARC architecture

Optimization techniques of on-chip memory system based on Ul...

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Anwen Huang Jun Gao Chaochao Feng Minxuan Zhang Key Laboratory of Science and Technology of National Defense of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China

It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary element of on-chip memory system is simulated by ModelSim and synthesized by Synopsys Design Complier with 90 nm standard cell library. Aimed at the potential limiting factor of improving the performance of memory hierarchy, corresponding optimization techniques of critical elements in memory system are explored finally.

关键词： System-on-a-chip Elliptic curve cryptography Hardware Costs Algorithm design and analysis Random access memory Clocks Registers Elliptic curves Protection

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