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Window memory layout scheme for alternate row-wise/column-wise matrix access

Window memory layout scheme for alternate row-wise/column-wi...

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作者： Guo, Lei Tang, Yuhua Dou, Yong Lei, Yuanwu Ma, Meng Zhou, Jie National Laboratory for Parallel and Distribution Processing National University of Defense Technol-ogy Changsha China

The effective bandwidth of the dynamic random-access memory (DRAM) for the alternate row-wise/column-wise matrix access (AR/CMA) mode, which is a basic characteristic in scientific and engineer-ing applications, is very low. Therefore, we propose the window memory layout scheme (WMLS), which is a matrix layout scheme that does not re-quire transposition, for AR/CMA applications. This scheme maps one row of a logical matrix into a rectangular memory window of the DRAM to balance the bandwidth of the row- and column-wise matrix access and to increase the DRAM 10 bandwidth. The optimal window configuration is theoretically analyzed to minimize the total number of no-data-visit oper-ations of the DRAM. Different WMLS implementationsare presented ac-cording to the memory structure of field-programmable gata array (FPGA), CPU, and GPU platforms. Experimental results show that the proposed WMLS can significantly improve DRAM bandwidth for AR/CMA appli-cations, achieved speedup factors of 1.6x and 2.0x are achieved for the general-purpose CPU and GPU platforms, respectively. For the FPGA plat-form, the WMLS DRAM controller is custom. The maximum bandwidth for the AR/CMA mode reaches 5.94 GB/s, which is a 73.6% improvement compared with that of the traditional row-wise access mode. Finally, we apply WMLS scheme for Chirp Scaling SAR application, comparing with the traditional access approach, the maximum speedup factors of 4.73X, 1.33X and 1.56X can be achieved for FPGA, CPU and GPU platform, re-spectively. © 2013 The Institute of Electronics, Information and Communication Engineers.

关键词： Graphics processing unit

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A pipelining strategy for accelerating convolution neural networks on ARM CPUs

A pipelining strategy for accelerating convolution neural ne...

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作者： Zhou, Xin Dou, Yong Li, Rongchun Zhang, Peng Liu, Yuntao National Key Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha China

Convolution is a primary operation in convolution neural networks. The speed of inference is mainly decided by the speed of the convolutional layer. Improving the performance of embedded processors makes it possible to process the inference on embedded devices. In this article, a pipelining strategy of single instruction and multiple data (SIMD) instructions is proposed to finely optimize the process of the 3 × 3 convolution on ARM-based CPUs. We implement the SIMD group to improve the efficiency of the SIMD pipeline. A tiling method is exploited to increase data reuse during the process. An evaluation model is proposed to guide the design of the tiling method and register allocation. The speed of our implementation is 5.18 times of the GNU compiler collection compiled unoptimized version on RK3288. The effect of our optimizing method is measured by a performance profiling tool, the performance information suggests that the pipelining strategy has a significant effect for both normal and depthwise separable convolution. By implementing multithread processing, the speedup achieves 18.3 compared with the single thread unoptimized version. © 2021 John Wiley & Sons Ltd

关键词： Convolution

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A parallel turbo product codes decoder based on graphics processing units 21

A parallel turbo product codes decoder based on graphics pro...

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21st IEEE International Conference on High Performance Computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Zhou, Xin Li, Rongchun National Key Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781728120584

Turbo product codes (TPC) are a class of forward error correction (FEC) codes. They have good bit error rate (BER) performance at high code rate. It is relatively simple to implement the encoder of TPC and the decoding complexity of their decoder is reasonable. Therefore, TPC are widely used in various places such as satellite communication systems and data storage systems. In this paper, a parallel TPC decoder based on GPUs is proposed. All rows or columns of the two-dimensional product code matrix are decoded simultaneously in this proposed decoder. A parallel elementary decoder is designed to simplify the decoding process of TPC which are constructed by extended Hamming codes. The calculations of test patterns and valid codewords are parallelled to reduce decoding latency. In order to further improve the decoding throughput, we present the multi-channels TPC decoder. The performance of the parallel decoder is measured on different GPUs. The experiment result shows that the decoding latency is reduced significantly compared with the TPC decoder based on a CPU. In addition, throughputs of proposed GPU decoder achieve 30Mbps on Nvidia RTX 2080 Ti and 38 Mbps on Nvidia Titan V, which are 44 times and 54 times of the CPU-based decoder. © 2019 IEEE.

关键词： Graphics processing unit

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A pipelining strategy for accelerating convolutional networks on arm processors 10th

A pipelining strategy for accelerating convolutional network...

引用

10th International Symposium on parallel Architectures, Algorithms and Programming, PAAP 2019

作者： Zhou, Xin Li, Rongchun Zhang, Peng Liu, Yuntao Dou, Yong National Key Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha450001 China

Convolutional neural networks (CNN) is playing an important role in many fields. Many applications are able to run the inference process of CNN with pre-trained models on mobile devices in these days. Improving performance of embedded processors such as ARM-based CPUs makes it possible to meet the requirement of real-time processing. In this paper, a pipelining strategy is proposed to accelerate convolution networks on ARM processors. We implement a 3 × 3 convolution with Neon instructions which are single instruction and multiple data (SIMD) instructions supported by ARM processors. In order to reduce stalls in the pipeline, issue orders of instructions are rearranged according to the out-of-order execution and dual-issue mechanism on ARM processors. A tiling method is exploited to increase data reuse. The input feature map is divided into multiple 6 × 6 tiles, and the computations within the tile is highly optimized using our proposed pipelining strategy. The speedup of proposed method is 2.88 compared with gcc compiled codes on RK3288. The effect of our optimizing method is measured by a performance profiling tool, cycles and cache misses are decreased significantly. The multi-thread version implemented with openMP achieve speedup of 6.8 compared with single-thread gcc complied version. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Pipelines

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A Novel Design of Flexible Crypto Coprocessor and Its Application

A Novel Design of Flexible Crypto Coprocessor and Its Applic...

引用

10th Annual Conference of Advanced Computer Architecture, ACA 2014

作者： Ni, Shice Dou, Yong Chen, Kai Deng, Lin National Laboratory for Parallel and Distribution Processing National University of Defense Technology Deya Road 109# Changsha 410073 China

ISBN: (纸本)9783662444900

Accelerating security protocols has been a great challenge in general-purpose processor due to the complexity of crypto algorithms. Most crypto algorithms are employed at the function level among different security protocols. We propose a novel flexible crypto coprocessor architecture that relies on Reconfigurable Cryptographic Blocks (RCBs) to achieve a balance between high performance and flexibility and implement the architecture for security application on FPGA. The pipelining technique is adopted to realize parallel data and to reduce the commication costs. We consider several crypto algorithms as examples to illustrate the design of the RCB in the FC Coprocessor. Finally, we create a prototype of the FC coprocessor on a Xilinx XC5VLX330 FPGA chip. The experiment results show that the coprocessor, running at 216 MHz, outperforms the software-based file encryption running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 29× for typical encrypt application. © Springer-Verlag Berlin Heidelberg 2014.

关键词： Coprocessor

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Optical on-chip networks with low-trimming-power

Optical on-chip networks with low-trimming-power

引用

Asia Communications and Photonics Conference, ACPC 2014

作者： Zhang, Luo Kefie, Wang Zhengbin, Pang Liquan, Xiao Weixia, Xu College of Computer National University of Defense Technology Changsha410073 China National Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha410073 China

The trimming power of on-chip optical networks consisted by 105 microrings is simulated. The total trimming power is no larger than 14W from 20°C to 100°C, if the distribution of these rings is optimized. &#... 详细信息

ISBN: (纸本)9781557528520

关键词： Trimming

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Low-trimming-power design of on-chip optical networks

Low-trimming-power design of on-chip optical networks

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Photonic Networks and Devices, 2014

作者： Zhang, Luo Kefie, Wang Zhengbin, Pang Weixia, Xu School of Computer Science National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781557527370

关键词： Fiber optic networks

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Implementation of parallel sparse Cholesky factorization on GPU

Implementation of parallel sparse Cholesky factorization on ...

引用

International Conference on Computer Science and Network Technology (ICCSNT)

作者： Dan Zou Yong Dou National Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781467329637

Direct methods for solving large sparse symmetric positive-definite linear systems of equations are popular because of their generality and robustness. The main bottleneck is the sparse Cholesky factorization, which exhibits irregular memory access behavior and unbalanced workload. In the past 10 years, many sparse Cholesky factorization algorithms have emerged, exploiting new architectural features. However, programming techniques currently employed on these platforms are not sufficient to implement sparse Cholesky factorization on many-core graphics processing units (GPUs) due to mismatches between irregular problem structures and single-instruction multiple-thread GPU architectures. In the present paper, we propose a task-based software approach for the parallel sparse Cholesky factorization aimed at heterogeneous computing platforms with GPU accelerators. The tasks are generated by CPU. An efficient task-scheduling mechanism guarantees the correct ordering of task execution and ensures a load balanced execution on GPU. Comparisons are made with the existing solver using problems arising from a range of practical applications. The experiment results show that the proposed approach can substantially improve the performance of sparse Cholesky factorization on GPU with 2.7×-4× speedup.

关键词： Sparse Cholesky factorization GPU Cholesky factorisation Graphics processing Unit GRAPPER PICK UP Task execution

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Optimization and Performance Modeling of Stencil Computations on ARM Architectures 22

Optimization and Performance Modeling of Stencil Computation...

引用

22nd IEEE International Conference on High Performance Computing and Communications, 18th IEEE International Conference on Smart City and 6th IEEE International Conference on Data Science and Systems, HPCC-SmartCity-DSS 2020

作者： Zhang, Kaifang Su, Huayou Zhang, Peng Dou, Yong National University of Defense Technology National Key Laboratory for Parallel and Distribution Processing Changsha China Caep Software Center for High Performance Numerical Simulation Beijing China Institute of Applied Physics and Computational Mathematics Beijing China

ISBN: (纸本)9781728176499

Stencil Computation has long been an omnipresent kernel of a wide range of scientific and engineering applications. There is much work investigating the stencil performance on x86 processors and accelerators such as GPU. Meanwhile, ARM processors for HPC have been highlighted more and more with Fugaku of Japan becoming the first number one system on the TOP-500 list. In this paper, we focus on modeling and optimizing the performance of stencil computation on ARM architectures. Specifically, we proposed a performance model for stencil computation based on tiling optimization to guide the optimal configuration of tiling parameters for good cache reuse. We validate the proposed model with the Performance Monitor Unit (PMU) provided by the ARM processor. Experimental results show that the prediction error of the execution time can be lower to 1.37%. Furthermore, we can achieve a maximum of 1.26 \times speedup compared to the naive implementation according to the optimization parameters provided from the model. © 2020 IEEE.

关键词： ARM processors

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An Efficient parallel Successive Cancellation List Polar Decoder Based on GPUs

An Efficient Parallel Successive Cancellation List Polar Dec...

引用

IEEE International Conference on Big Data and Cloud Computing (BdCloud)

作者： Xin Zhou Rongchun Li Shijie Li Yuntao Liu Yong Dou National Key Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha China

ISBN: (数字)9781728143286

ISBN: (纸本)9781728143293

Polar codes are a class of codes that can achieve the symmetric capacity. They are adopted to be control code for the enhanced mobile broadband (eMBB) for the fifth generation(5G) standard. Although Polar codes can be efficiently decoded by successive cancellation algorithm with complexity O(NlogN), decoding performance of this algorithm is not good enough for short codewords. The successive cancellation list(SCL) decoder is recently investigated in most studies. It has better frame error rate(FER) performance but poor latency and throughput. In this study, a parallel SCL decoder based on the graphic processing unit(GPU) is designed to reduce the latency and improve the decoding throughput. An efficient approach for sharing the intermediate values among different decoding paths is introduced. This method reduces the computing complexity and decoding latency. The implementation of parallel non-recursive decoding algorithm also increases the throughput significantly. For the typical case of code length N=1024 and list size L=4 with code rate R = 0.5, the parallel decoder based on GPU achieves throughput of 49 Mbps on Nvidia GTX 980 and 79 Mbps on Nvidia Titan X. The throughputs are 240 and 392 times higher than the decoder based on the CPU.

关键词： Decoding Polar codes Throughput Graphics processing units Measurement Complexity theory Reliability

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