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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Zhao, Zeyu Cai, Zhikuang Technology College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Nanjing China

ISBN: (纸本)9798350304510

In recent years, with the development of post-Moore era, integrated circuit architecture is complex and test cost is increasing. How to apply efficient, reliable, fast and sustainable ideas to integrated circuit design has become a research hotspot in this field. Machine Learning, by virtue of its ability to quickly process abundant data information, shines in the field of Design For Test, which aims to improve the reliability of integrated circuit products and reduce design costs. In this paper, we introduce the application of Machine Learning in scan compression, Automatic Test Pattern Generation algorithm, the Test Pattern Generator in Built-In-Self-Test and test power. In addition, we prospect the foreground application of Machine Learning application in scan test, Automatic Test Pattern Generation, Built-In-Self-Test and test power. © 2023 IEEE.

关键词： Machine learning

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Enhanced back-illuminated Ga_(2)O_(3)-based solar-blind ultraviolet photodetectors

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Science China(Technological Sciences) 2024年第11期67卷 3477-3484页

作者： YAN ZuYong ZHI YuSong JI XueQiang YUE JianYing WANG JinJin LIU Zeng LI Shan LI PeiGang HOU ShangLin WU Gang LEI JingLi TANG WeiHua School of Science State Key Laboratory of Advanced Processing and Recycling of Nonferrous MetalsLanzhou University of TechnologyLanzhou 730050China China Academy of Launch Vehicle Technology Beijing 100076China School of Integrated Circuits&State Key Laboratory of Information Photonics and Optical Communications Beijing University of Posts and TelecommunicationsBeijing 100876China School of Electronic Information Engineering Inner Mongolia UniversityHohhot 010021China College of Electronic and Optical Engineering&College of Microelectronics National and Local Joint Engineering Laboratory for RF Integration and Micro-Packing TechnologiesNanjing University of Posts and TelecommunicationsNanjing 210023China

Ga_(2)O_(3)is a promising material for deep-ultraviolet(DUV)photodetectors due to its ultra-wide bandgap and high thermal and chemical ***,because of their relatively low responsivity,Ga_(2)O_(3)-based photodetectors still have difficulty meeting the requirements of practical ***,we construct a high-performance Ga_(2)O_(3)photodetector realized by *** high-crystallinity epitaxially grown Ga_(2)O_(3)as the DUV absorbing layer and the double-polished Al_(2)O_(3)substrate as the transparent window for injection of photons,the device operating in the back-illuminated mode exhibits a higher DUV photoresponse and faster response speed than in the front-illuminated ***,our experimental results have led to the development of a novel strategy for designing and fabricating high-performance Ga_(2)O_(3)photodetectors.

关键词： Ga_(2)O_(3) back-illuminated solar-blind photodetector

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Tradeoff between the Breakdown Voltage and Specific On-Resistance of SOI RESUrf LDMOS 15

Tradeoff between the Breakdown Voltage and Specific On-Resis...

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15th IEEE International Conference on ASIC, ASICON 2023

作者： Guo, Yufeng Yang, Kemeng Chen, Jing Li, Man Jiang, Zhengfei Yao, Jiafei Zhang, Jun Zhang, Maolin Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210023 China

ISBN: (纸本)9798350312980

The tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp) is an important issue for the power device. Baliga's Figure of Merits (BFOM) and silicon limit both are useful tools to evaluate this relationship. However, the strong 2-D effect is not considered in the conventional BFOM and the present silicon limit. In this paper, a new BFOM model of SOI RESUrf LDMOS is proposed based on the formulized 2-D electric field in the drift region. Then, the device structure parameters are optimized to maximize the BFOM. A novel silicon limit and critical electric field are also derived. The differences between the lateral and the vertical devices are investigated and compared. The mechanism is discussed. The simulation based on the TCAD tool is employed to verify the novel BFOM and silicon limit. © 2023 IEEE.

关键词： BFOM Breakdown voltage LDMOS RESUrf Silicon limit SOI Specific on-resistance

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Complete Timing Model of ECSM Lookup Table for CMOS Inverter 8

Complete Timing Model of ECSM Lookup Table for CMOS Inverter

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Wang, Jiawei Guo, Jingjing Zhao, Dongmin Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

In the early days, engineers used non-linear delay models (NLDM) to estimate the circuit delay information. However, the accuracy of NLDM lookup table (LUT) decreases with the continuous change of the process, which makes the delay estimation become a difficult problem. Therefore, the effective current source model (ECSM) is proposed. The ECSM is a LUT composed of input transition time (TR) and load capacitance (CL), which can save the threshold crossing point (TCP) of the output waveform to better estimate the delay. However, the timing model is needed to reduce re-presentations, due to the high cost of building the library of ECSM. In this work, we present a timing model of the complete ECSM LUT for a CMOS inverter. The timing model is divided into two cases with a total of five regions. The proposed timing model is further analyzed by judging the value of threshold crossing points' voltage (VTCP) and drain to source saturation voltage (Vdsat), and the model is simplified for different threshold crossing points. Compared with the simulation results of HSPICE, the model is accurate with a maximum error of 2.35% and a maximum average error of 0.45%, which reduces the repetitive simulation of HSPICE. © 2023 IEEE.

关键词： Table lookup

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A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide Input Range of 4.5-35V 8

A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide ...

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Du, Yifei Wang, Xin Wu, Wei Han, Zhenhua Qi, Zhiwei Wang, Zixuan Hu, ShanWen Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

This work presents a high-precision and wide-input-range reference voltage source based on a 180nm BCD process. The reference voltage source generates a constant voltage of 2.5V under the supply voltage ranging from 4.5V to 35V. Both a pre-regulator with current extraction, and high-order curvature compensation are proposed in this work. The current extraction circuit greatly improves the stability of output voltage, and the high-order term of VBE in Bipolar Junction Transistor (BJT) is used for temperature compensation to achieve an output voltage with a low temperature coefficient. Simulation results show that a line regulation of 14ppm/V is achieved, and an average temperature coefficient is 1.5ppm/°C over the range of -45°C to 125°C. In addition, the Power Supply Rejection Ratio (PSRR) is 102.82dB at 10Hz. © 2023 IEEE.

关键词： Temperature

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A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure 8

A High-Precision Delay Faults Testing Technique Based on the...

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Liu, Xiaoting Zhang, Xuewei Hong, Haofei Zhou, Guopeng Wang, Zixuan Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced. © 2023 IEEE.

关键词： Frequency converters

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A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution 8

A Wide-Range and High-Linearity Timing Generator with 1.25ps...

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Chen, Tianyang Wang, Qianyu Wang, Ze Qi, Zhiwei Han, Zhenhua Liu, Lu Hu, Shanwen Nanjing University of Posts and Telecommunications College of Intergrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of -20 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB. © 2023 IEEE.

关键词： Phase locked loops

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Wide Stopband Substrate Integrated Waveguide Filter Using Bisection and Trisection Coupling in Multilayer

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Chinese Journal of Electronics 2024年第2期33卷 436-442页

作者： Peng CHU Jianguo FENG Peng ZHU Lei GUO Long ZHANG Leilei LIU Guoqing LUO Ke WU College of Electronic and Optical Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology School of Information and Communication Engineering Dalian University of Technology Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-sen University College of Electronics and Information Engineering Shenzhen University School of Electronics and Information Hangzhou Dianzi University Poly-Grames Research Center Polytechnique Montreal

This article presents a highly efficient method for substrate-integrated-waveguide（SIW） filters to achieve very wide stopbands. By employing the proposed trisection slots in addition to the bisection slots as the inter-coupling structures, all spurious modes below TE505 of a SIW filter working in the fundamental mode TE101（f0）can be eliminated without requiring additional structure or complex theoretical analysis, without affecting the design of the fundamental passbands, and without degrading the performance of the filters. For verification, two prototype filters are designed, fabricated, and measured with wide stopbands up to 4.15f0 and 4.83f0, respectively. The proposed technique could facilitate the development of high-performance wide-stopband SIW filters for microwave/wireless circuits and systems.

关键词： Bandpass filter Wide stopband Substrate integrated waveguide Spurious mode suppression Multilayer

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Multi-Instantiation Top-Level Routing Technique Based on Decision Negotiation Algorithm 6

Multi-Instantiation Top-Level Routing Technique Based on Dec...

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6th International Conference on Electronics Technology, ICET 2023

作者： Yang, Hang Zhang, Xuewei Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing210003 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing210003 China

ISBN: (纸本)9798350337693

With the development of integrated circuit, multi-instantiated block technology is considered as a reliable optimization direction of chip design, which can effectively save the storage and labor cost in the development process, but brings new challenges to the top layer routing at the same time. On this basis, a multi-instantiation top-level routing algorithm based on decision negotiation is designed in this paper, which effectively solves the problems of multi-instantiated block routing, including long routing time and too long path length. In this paper, a non-uniform grid form is proposed to formulate alternative path sets and determine alternative routing channels between endpoints. The decision extraction and decision evaluation algorithms are used to deal with the path redundancy and short circuit problems generated by multiple instantiations. The feasible solution is determined by improved BFS (Breadth First Search) algorithm on the candidate decision set. The optimal solution with the shortest path in Manhattan is determined by iterative decision evaluation in the feasible solution. In order to verify the accuracy and effectiveness of the proposed method, a verification experiment is conducted in this paper for a number of multi-instantiation modules within 100. The experimental results show that the routing time of the proposed multi-instantiation top-level routing algorithm based on decision negotiation is between 0.1s and 3s, and the ratio of the path length to the standard value is over 95%, on the basis of a 100% success ratio. © 2023 IEEE.

关键词： Routing algorithms

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Multi-instantiated Block Top-layer Routing Technique Based on Steiner Tree Algorithm

Multi-instantiated Block Top-layer Routing Technique Based o...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Yang, Hang Chen, Junyuan Cai, Zhikuang Guo, Jingjing Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing210003 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210003 China

ISBN: (纸本)9798350304510

As the scale of chips becomes larger and larger, the time and labor cost of the overall design of a large single chip becomes higher and higher. Therefore, it has become a widely adopted solution to divide one large-scale design into several smaller blocks and realize the functions of each block respectively. In this paper, a multi-instantiated block routing technique is proposed based on the improved Steiner tree algorithm. The algorithm divides wire networks into grids and uses FLUTE to construct and decompose the minimum rectangular Steiner tree of all multipin wire networks, which will decompose any multi-pin connection into several two-pin connections. It abstracts the functions of multi-instantiated blocks involved, and adds fixed pins on the edge of them. The routing process will be conducted inside every block respectively. In order to verify the accuracy and validity of the proposed method, a series of verification experiments are carried out, which shows that the proposed multi-instantiated block routing algorithm can effectively reduce the path redundancy caused by multiple pass-throughs in blocks and improve the routing process efficiency. © 2023 IEEE.

关键词： Routing algorithms

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