检索结果-内蒙古大学图书馆

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

引用

Chinese Physics B 2020年第3期29卷 460-467页

作者： Jia-Fei Yao Yu-Feng Guo Zhen-Yu Zhang Ke-Meng Yang Mao-Lin Zhang Tian Xia College of Electronic and Optical Engineering&College of Microelectronics Nanjing University of Posts and TelecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing 210023China School of Electrical Engineering University of VermontBurlingtonVT 05405USA

This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.

关键词： high-k dielectric step doped silicon pillar model breakdown voltage

来源：评论

学校读者我要写书评

暂无评论

Review of the SiC LDMOS power device

引用

Journal of Semiconductors 2024年第8期45卷 4-17页

作者： Ziwei Hu Jiafei Yao Ang Li Qi Sun Man Li Kemeng Yang Jun Zhang Jing Chen Maolin Zhang Yufeng Guo College of Integrated Circuit Science and Engineering(Industry-Education Integration School) Nanjing University of Posts andT elecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing 210023China Nantong Institute of Nanjing University of Posts and Telecommunications Nantong 226000China

Silicon carbide(SiC),as a third-generation semiconductor material,possesses exceptional material properties that significantly enhance the performance of power *** SiC lateral double-diffused metal–oxide–semiconductor(LDMOS)power devices have undergone continuous optimization,resulting in an increase in breakdown voltage(BV)and ultra-low specific on-resistance(Ron,sp).This paper has summarized the structural optimizations and experimental progress of SiC LDMOS power devices,including the trench-gate technology,reduced surface field(RESUrf)technology,doping technology,junction termination techniques and so *** paper is aimed at enhancing the understanding of the operational mechanisms and providing guidelines for the further development of SiC LDMOS power devices.

关键词： SiC LDMOS specific on-resistance breakdown voltage

来源：评论

学校读者我要写书评

暂无评论

An Active Gate Driver with Controllable Gate Current for SiC MOSFETs 9

An Active Gate Driver with Controllable Gate Current for SiC...

引用

9th International Conference on Integrated Circuits and microsystems, ICICM 2024

作者： Jiang, Zhengfei Yao, Jiafei Dai, Yuxuan Hu, Ziwei Li, Man Zhang, Yi Wang, Zixuan Cai, Zhikuang Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798331509453

An active gate driver (AGD) with controllable gate current (CGC) for SiC MOSFETs is proposed to reduce voltage overshoots and current overshoots. In the CGC-AGD, the controllable current overshoot suppression circuit and voltage overshoot suppression circuit are designed to control the rate of changes in current (di/dt) and voltage (dv/dt) to effectively reduce overshoots. Meanwhile, the current conversion circuit and the push-pull amplifier circuit compensate for the current reduction resulting from the overshoot suppression. This paper simulated the current and voltage overshoot during the switching process based on a double pulse test set up with a 1200V SiC MOSFET by LTspice software. The simulation results show that the current overshoot was reduced by 60% and the voltage overshoot was reduced by 22% when compared to the conventional gate driver (CGD). While compared with the AGD circuit, the current overshoot of CGC-AGD is reduced by 26% and the voltage overshoot is reduced by 19%. These results demonstrate that the CGC-AGD has better suppress on current and voltage overshoot. © 2024 IEEE.

关键词： MOSFET devices

来源：评论

学校读者我要写书评

暂无评论

A Review of Intelligent Design for Test Based on Machine Learning

A Review of Intelligent Design for Test Based on Machine Lea...

引用

2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Zhao, Zeyu Cai, Zhikuang Technology College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Nanjing China

ISBN: (纸本)9798350304510

In recent years, with the development of post-Moore era, integrated circuit architecture is complex and test cost is increasing. How to apply efficient, reliable, fast and sustainable ideas to integrated circuit design has become a research hotspot in this field. Machine Learning, by virtue of its ability to quickly process abundant data information, shines in the field of Design For Test, which aims to improve the reliability of integrated circuit products and reduce design costs. In this paper, we introduce the application of Machine Learning in scan compression, Automatic Test Pattern Generation algorithm, the Test Pattern Generator in Built-In-Self-Test and test power. In addition, we prospect the foreground application of Machine Learning application in scan test, Automatic Test Pattern Generation, Built-In-Self-Test and test power. © 2023 IEEE.

关键词： Machine learning

来源：评论

学校读者我要写书评

暂无评论

Circularly polarized leaky wave antenna based on compound left-right-hand structure 13

Circularly polarized leaky wave antenna based on compound le...

引用

13th International Conference on microwave and Millimeter Wave technology, ICMMT 2021

作者： Yin, Huanyu Li, Pinyan Liu, Leilei National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology College of Electronic and Optical Engineering Nanjing University of Posts and Telecommunications Nanjing210003 China

ISBN: (纸本)9781665434379

In this paper, a circularly polarized leaky wave antenna based on compound left-right-hand structure (CRLH) is proposed. In this design, the equivalent series capacitance is realized by the annular groove on the metal microstrip, and the parallel inductance is realized by the metal through hole. The antenna can realize frequency beam scanning in 14-18GHz and circular polarization in 15.5-18GHz. © 2021 IEEE.

关键词： Traveling wave antennas

来源：评论

学校读者我要写书评

暂无评论

A Scalable Model for On-Chip Interdigital Capacitor Based on Space-Mapping Neural Network 9

A Scalable Model for On-Chip Interdigital Capacitor Based on...

引用

9th International Conference on Integrated Circuits and microsystems, ICICM 2024

作者： Xiong, Yuqing Guo, Siqing Hu, Shanwen Gu, Yan Fang, Yuming Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory RF Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798331509453

A scalable model for on-chip interdigital capacitor is proposed based on space-mapping neural network (SMNN), which combines the equivalent circuit of capacitor and perceptron neural network. By expanding the traditional series equivalent circuit into a π-type structure and adding a series network of resistor and capacitor to characterize the coupling effect, the variation of the equivalent series resistance (ESR) and S-parameter with frequency can be effectively predicted. According to the mathematical equation, the value of each component for the 1-π equivalent circuit model can be quickly and correctly obtained. In order to effectively improve the prediction accuracy and convergence speed of neural network, Particle Swarm Optimization (PSO) and Levenberg-Marquardt Back Propagation (LMBP) are used to select and optimize the weights and thresholds of the neural networks. Compared with the traditional neural network model, the proposed SMNN reduces the number of neurons required to map the input-output nonlinear relationship, so that the modeling time is only reduced to 10 ∼ 15 seconds, and the test data accuracy is good. © 2024 IEEE.

关键词： Particle swarm optimization (PSO)

来源：评论

学校读者我要写书评

暂无评论

Tradeoff between the Breakdown Voltage and Specific On-Resistance of SOI RESUrf LDMOS 15

Tradeoff between the Breakdown Voltage and Specific On-Resis...

引用

15th IEEE International Conference on ASIC, ASICON 2023

作者： Guo, Yufeng Yang, Kemeng Chen, Jing Li, Man Jiang, Zhengfei Yao, Jiafei Zhang, Jun Zhang, Maolin Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210023 China

ISBN: (纸本)9798350312980

The tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp) is an important issue for the power device. Baliga's Figure of Merits (BFOM) and silicon limit both are useful tools to evaluate this relationship. However, the strong 2-D effect is not considered in the conventional BFOM and the present silicon limit. In this paper, a new BFOM model of SOI RESUrf LDMOS is proposed based on the formulized 2-D electric field in the drift region. Then, the device structure parameters are optimized to maximize the BFOM. A novel silicon limit and critical electric field are also derived. The differences between the lateral and the vertical devices are investigated and compared. The mechanism is discussed. The simulation based on the TCAD tool is employed to verify the novel BFOM and silicon limit. © 2023 IEEE.

关键词： BFOM Breakdown voltage LDMOS RESUrf Silicon limit SOI Specific on-resistance

来源：评论

学校读者我要写书评

暂无评论

Compact SPAD pixels with fast and accurate photon counting in the analog domain

引用

Journal of Semiconductors 2021年第5期42卷 85-90页

作者： Zhiqiang Ma Zhong Wu Yue Xu College of Electronic and Optical Engineering&College of Microelectronics Nanjing University of Posts and TelecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory of RF integration&Micro-Assembly Technology Nanjing 210023China

A compact pixel for single-photon detection in the analog domain is presented. The pixel integrates a single-photon avalanche diode(SPAD), a passive quenching & active recharging circuit(PQARC), and an analog counter for fast and accurate sensing and counting of photons. Fabricated in a standard 0.18 μm CMOS technology, the simulated and experimental results reveal that the dead time of the PQARC is about 8 ns and the maximum photon-counting rate can reach 125 Mcps(counting per second). The analog counter can achieve an 8-bit counting range with a voltage step of 6.9 mV. The differential nonlinearity(DNL) and integral nonlinearity(INL) of the analog counter are within the ± 0.6 and ± 1.2 LSB, respectively, indicating high linearity of photon counting. Due to its simple circuit structure and compact layout configuration, the total area occupation of the presented pixel is about 1500 μm^(2), leading to a high fill factor of 9.2%. The presented in-pixel front-end circuit is very suitable for the high-density array integration of SPAD sensors.

关键词： single-photon avalanche diode(SPAD) passive quenching&active recharging circuit(PQARC) analog counter nonlinearity

来源：评论

学校读者我要写书评

暂无评论

Design of Dual-band Implantable Antenna with Shorting Pins 8

Design of Dual-band Implantable Antenna with Shorting Pins

引用

8th Asia-Pacific Conference on Antennas and Propagation, APCAP 2019

作者： Hua, Dengyu Jin, Xiaoyu Xu, Li-Jie Duan, Zhu Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China Southeast University State Key Laboratory of Millimeter Waves Nanjing China

ISBN: (纸本)9781665400541

This paper proposes a pin-loaded dual-band antenna for implantable applications, covering both 915 MHz Industrial, Scientific and Medical (ISM) band and 1.4 GHz Wireless Medical Telemetry Service (WMTS) band. With two shorting pins loaded at two corners, miniaturization is achieved. Furthermore, four straight slots are introduced on the top patch, giving rise to the appearance of two resonances for dual-band operation. To achieve better impedance matching, another three open-end L-shaped slots are etched on the ground, and the final proposed antenna is well matched at two required bands. © 2019 IEEE.

关键词： microwave antennas

来源：评论

学校读者我要写书评

暂无评论

Complete Timing Model of ECSM Lookup Table for CMOS Inverter 8

Complete Timing Model of ECSM Lookup Table for CMOS Inverter

引用

8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Wang, Jiawei Guo, Jingjing Zhao, Dongmin Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

In the early days, engineers used non-linear delay models (NLDM) to estimate the circuit delay information. However, the accuracy of NLDM lookup table (LUT) decreases with the continuous change of the process, which makes the delay estimation become a difficult problem. Therefore, the effective current source model (ECSM) is proposed. The ECSM is a LUT composed of input transition time (TR) and load capacitance (CL), which can save the threshold crossing point (TCP) of the output waveform to better estimate the delay. However, the timing model is needed to reduce re-presentations, due to the high cost of building the library of ECSM. In this work, we present a timing model of the complete ECSM LUT for a CMOS inverter. The timing model is divided into two cases with a total of five regions. The proposed timing model is further analyzed by judging the value of threshold crossing points' voltage (VTCP) and drain to source saturation voltage (Vdsat), and the model is simplified for different threshold crossing points. Compared with the simulation results of HSPICE, the model is accurate with a maximum error of 2.35% and a maximum average error of 0.45%, which reduces the repetitive simulation of HSPICE. © 2023 IEEE.

关键词： Table lookup

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：