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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Tianyang Chen Qianyu Wang Ze Wang Zhiwei Qi Zhenhua Han Lu Liu Shanwen Hu College of Intergrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of −20 ~ 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB.

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Multi-Instantiation Top-Level Routing Technique Based on Decision Negotiation Algorithm

Multi-Instantiation Top-Level Routing Technique Based on Dec...

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International Conference on Electronics technology (ICET)

作者： Hang Yang Xuewei Zhang Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

With the development of integrated circuit, multi-instantiated block technology is considered as a reliable optimization direction of chip design, which can effectively save the storage and labor cost in the development process, but brings new challenges to the top layer routing at the same time. On this basis, a multi-instantiation top-level routing algorithm based on decision negotiation is designed in this paper, which effectively solves the problems of multi-instantiated block routing, including long routing time and too long path length. In this paper, a non-uniform grid form is proposed to formulate alternative path sets and determine alternative routing channels between endpoints. The decision extraction and decision evaluation algorithms are used to deal with the path redundancy and short circuit problems generated by multiple instantiations. The feasible solution is determined by improved BFS (Breadth First Search) algorithm on the candidate decision set. The optimal solution with the shortest path in Manhattan is determined by iterative decision evaluation in the feasible solution. In order to verify the accuracy and effectiveness of the proposed method, a verification experiment is conducted in this paper for a number of multi-instantiation modules within 100. The experimental results show that the routing time of the proposed multi-instantiation top-level routing algorithm based on decision negotiation is between 0.1s and 3s, and the ratio of the path length to the standard value is over 95%, on the basis of a 100% success ratio.

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A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide Input Range of 4.5-35V

A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide ...

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Yifei Du Xin Wang Wei Wu Zhenhua Han Zhiwei Qi Zixuan Wang ShanWen Hu College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

This work presents a high-precision and wide-input-range reference voltage source based on a 180nm BCD process. The reference voltage source generates a constant voltage of 2.5V under the supply voltage ranging from 4.5V to 35V. Both a pre-regulator with current extraction, and high-order curvature compensation are proposed in this work. The current extraction circuit greatly improves the stability of output voltage, and the high-order term of V$_{\mathbf{BE}}$ in Bipolar Junction Transistor (BJT) is used for temperature compensation to achieve an output voltage with a low temperature coefficient. Simulation results show that a line regulation of 14ppm/V is achieved, and an average temperature coefficient is 1.5ppm/°C over the range of −45°C to 125°C. In addition, the Power Supply Rejection Ratio (PSRR) is 102.82dB at 10Hz.

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Multi-instantiated Block Top-layer Routing Technique Based on Steiner Tree Algorithm

Multi-instantiated Block Top-layer Routing Technique Based o...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Hang Yang Junyuan Chen Zhikuang Cai Jingjing Guo Yufeng Guo College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing CHN National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing CHN

As the scale of chips becomes larger and larger, the time and labor cost of the overall design of a large single chip becomes higher and higher. Therefore, it has become a widely adopted solution to divide one large-scale design into several smaller blocks and realize the functions of each block respectively. In this paper, a multi-instantiated block routing technique is proposed based on the improved Steiner tree algorithm. The algorithm divides wire networks into grids and uses FLUTE to construct and decompose the minimum rectangular Steiner tree of all multipin wire networks, which will decompose any multi-pin connection into several two-pin connections. It abstracts the functions of multi-instantiated blocks involved, and adds fixed pins on the edge of them. The routing process will be conducted inside every block respectively. In order to verify the accuracy and validity of the proposed method, a series of verification experiments are carried out, which shows that the proposed multi-instantiated block routing algorithm can effectively reduce the path redundancy caused by multiple pass-throughs in blocks and improve the routing process efficiency.

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Complete Timing Model of ECSM Lookup Table for CMOS Inverter

Complete Timing Model of ECSM Lookup Table for CMOS Inverter

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Jiawei Wang Jingjing Guo Dongmin Zhao Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In the early days, engineers used non-linear delay models (NLDM) to estimate the circuit delay information. However, the accuracy of NLDM lookup table (LUT) decreases with the continuous change of the process, which makes the delay estimation become a difficult problem. Therefore, the effective current source model (ECSM) is proposed. The ECSM is a LUT composed of input transition time (T R ) and load capacitance (C L ), which can save the threshold crossing point (TCP) of the output waveform to better estimate the delay. However, the timing model is needed to reduce re-presentations, due to the high cost of building the library of ECSM. In this work, we present a timing model of the complete ECSM LUT for a CMOS inverter. The timing model is divided into two cases with a total of five regions. The proposed timing model is further analyzed by judging the value of threshold crossing points’ voltage (V TCP ) and drain to source saturation voltage (V dsat ), and the model is simplified for different threshold crossing points. Compared with the simulation results of HSPICE, the model is accurate with a maximum error of 2.35% and a maximum average error of 0.45%, which reduces the repetitive simulation of HSPICE.

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Stage Delay Calculation Method Considering Effective Capacitance

Stage Delay Calculation Method Considering Effective Capacit...

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International Conference on Electronics technology (ICET)

作者： Peiwen Zha Jingjing Guo Shugang Zhang College of Integrated Circuit Secience and Engineering National and Local Joint Engineering Laboratory of RF Intergration and Micro-assembly Technology Nanjing University of Posts and Telecommunication Nanjing China

ISBN: (数字)9798350363951

ISBN: (纸本)9798350363968

A key part of a static timing tool is its delay calculation engine-responsible for computing delay, slew, and waveform information from models of logic gates and interconnect parasitic. A stage delay calculator includes cell delay and wire delay. In previous studies, they are often independent. With the advancement of technology, the Miller effect and highly resistive load interconnect have increased the interdependency between cell and wire delay calculations. In this paper, we propose a stage delay calculation approach that utilizes effective capacitance(Ceff) to address the computation of delays and waveforms for both cells and wires. Furthermore, machine learning is employed in the calculation of wire delay, modeling the interconnects using Ceffs as a feature. Experimental results demonstrate that the proposed delay calculation method achieves an accuracy within 1.66% of the delays calculated by SPICE.

关键词： Resistance Accuracy Computational modeling Machine learning Logic gates Capacitance SPICE

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A 13GS/s One-Bit ADC with 18GHz Analog Bandwith Based on InP DHBT technology 14

A 13GS/s One-Bit ADC with 18GHz Analog Bandwith Based on InP...

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14th IEEE International Conference on Solid-State and Integrated Circuit technology, ICSICT 2018

作者： Li, Xiaopeng Wang, Zhigong Zhang, Yi Zhang, Youtao Zhang, Min Institute of RF - OE ICs Southeast University Nanjing210096 China Nanjing GuoBo Electronics Co. Ltd Nanjing210016 China Nanjing Electronic Devices Institute Nanjing210016 China National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology Nanjing210046 China State Key Laboratory of Millimeter Waves Southeast University Nanjing210096 China Post-Doctoral Research Center JiangSu HengXin Technology Co. Ltd Yixing214222 China Science and Technology on Monolithic Intergrated Circuits and Modules Laboratory Nanjing210016 China

ISBN: (纸本)9781538644409

In this paper, an ultra-high-speed ultra-wide-bandwidth one-bit analog-to-digital converter (ADC) is implemented. The chip uses a latched high-sensitivity comparator to achieve one-bit quantization, and an integrated 1:8 demultiplexer to reduce the data rate of the output ports, which is helpful for system applications. The chip is implemented with a 0.7μm InP DHBT process. Measurement results show that the sampling rate of the chip is up to 13GS/s, the analog input bandwidth is greater than 18GHz, the input sensitivity is less than -25dBm, and the power consumption is 1.2W. © 2018 IEEE.

关键词： Indium phosphide

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A Thermo-mechanical Coupled 3D Crystal Plasticity Finite Element Model for CASTIN Solder Alloy

A Thermo-mechanical Coupled 3D Crystal Plasticity Finite Ele...

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International Conference on (ICEPT) Electronic Packaging technology

作者： Yang Li Yujie Cheng Shanwen Hu Binbin Xu Lu Liu Zhikuang Cai The College of Integrated Circuit Science and Engineering National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China Nantong Institute of Nanjing University of Posts and Telecommunications Nantong China

As one of the fragile components in the package structure, solder joints are usually subjected to thermo-mechanical coupled loads. Therefore, it is essential to investigate the deformation behavior and constitutive model of solder joints for the reliability prediction of the whole packaging. As a kind of polycrystalline material, solder joints contain multiple grains with different orientations. As the electronic devices gradually decrease in size, the solder joints may only contain one or several grains, the conventional macro-phenomenological constitutive model is not able to describe the deformation at the grain scale caused by crystalline slip. In this paper, a finite element model on the basis of 3D crystal plasticity theory is proposed, in which the behavior of each grain is first investigated, and the overall behavior of the structure is obtained by calculating the average of all elements. Firstly, the models with 10, 40, and 100 grains are established to find out the influence of grains’ numbers on the overall behavior. Then, the strain rate jump experiments of CASTIN solder alloy are simulated using the appropriate model. The CASTIN solder alloy is stretched to 1.5% strain at strain rates of 10 -6 s -1 to 10 -2 s -1 under temperatures of -55°C to 125°C, respectively. A comparison is made between the simulation results and the experimental results, the parameters of the established model are obtained through matching the experiment curves, and the effect of the temperature on the parameters is analyzed. The model then is used to investigate the deformation response of CASTIN alloy under the thermo-mechanical cycle tests without changing these parameters. It can be found that the proposed model can give reasonable predictions of CASTIN alloy under thermo-mechanical coupled loads.

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Achieving highly-efficient H2S gas sensor by flower-like SnO_(2)–SnO/porous GaN heterojunction

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Chinese Physics B 2023年第2期32卷 193-200页

作者：刘增都灵张少辉边昂方君鹏邢晨阳李山汤谨诚郭宇锋唐为华 College of Integrated Circuit Science and Engineering Nanjing University of Posts and TelecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory for RF Integration and Micro-Packing Technologies Nanjing University of Posts and TelecommunicationsNanjing 210023China School of Electronic and Information Engineering Jinling Institute of TechnologyNanjing 211169China Institute of Microscale Optoelectronics Shenzhen UniversityShenzhen 518060China Key Laboratory of Luminescence and Optical Information of Ministry of Education Institute of Optoelectronic TechnologyBeijing Jiaotong UniversityBeijing 100044China School of Integrated Circuits Tsinghua UniversityBeijing 100044China Key Laboratory of Optoelectronic Devices and Systems of Ministry of Education College of Physics and Optoelectronic EngineeringShenzhen UniversityShenzhen 518060China State Key Laboratory of Information Photonics and Optical Communications School of ScienceBeijing University of Posts and TelecommunicationsBeijing 100876China

A flower-like SnO_(2)–SnO/porous Ga N(FSS/PGaN) heterojunction was fabricated for the first time via a facile spraying process, and the whole process also involved hydrothermal preparation of FSS and electrochemical wet etching of GaN,and SnO_(2)–SnO composites with p–n junctions were loaded onto PGaN surface directly applied to H_(2)S sensor. Meanwhile,the excellent transport capability of heterojunction between FSS and PGaN facilitates electron transfer, that is, a response time as short as 65 s and a release time up to 27 s can be achieved merely at 150℃ under 50 ppm H_(2)S concentration, which has laid a reasonable theoretical and experimental foundation for the subsequent PGaN-based heterojunction gas *** lowering working temperature and high sensitivity(23.5 at 200 ppm H2S) are attributed to the structure of PGaN itself and the heterojunction between SnO_(2)–SnO and PGaN. In addition, the as-obtained sensor showed ultra-high test *** simple design strategy of FSS/PGaN-based H_(2)S sensor highlights its potential in various applications.

关键词： gas sensor SnO_(2)–SnO porous GaN heterojunction

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Energy Efficient Resource Allocation in NOMA-Sectored Heterogeneous Network

Energy Efficient Resource Allocation in NOMA-Sectored Hetero...

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International Conference on Wireless Communications and Signal Processing (WCSP)

作者： Lei Wang Wen Tang Ting Qi Jingwu Cui Baoyu Zheng Key Lab of Broadband Wireless Communication and Sensor Network Technology Nanjing University of Posts and Telecommunications Ministry of Education China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications China

ISBN: (数字)9781728172361

ISBN: (纸本)9781728172378

Non-orthogonal multiple access (NOMA) and heterogeneous network (HetNet) have been regarded as two promising technologies in 5G, which can support massive connectivity. Integrating NOMA technology into HetNet is an inevitable trend to achieve better spectral efficiency. However, interference control becomes more complicated due to the combination of these two technologies and the optimization of energy efficiency comes at the expense of spectral efficiency. Therefore, we develop a novel network scenario, which exploits the benefits of sectorization. In this paper, we aim to maximize the energy efficiency of the entire small cells in an uplink underlaying two-tier NOMA heterogeneous network with sectorization. Since this energy efficiency maximization problem is a mixed integer non-linear programming (MINLP) problem which is difficult to solve, it is decomposed into two subproblems. Firstly, we use the Lagrange dual method and Karush-Kuhn-Tucker (KKT) optimal conditions to obtain the closed-form power allocation solution. Secondly, a low-complexity subchannel allocation algorithm based on the greedy strategy is proposed. Simulation results show that our proposed scheme obtain significant energy efficiency gain and is superior to other existing schemes.

关键词： Resource management NOMA Uplink Base stations Heterogeneous networks Telecommunications Mathematical model

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