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A 10GS/s 0.13um SiGe Track-and-Hold Amplifier with 38GHz Analog Bandwidth 10

A 10GS/s 0.13um SiGe Track-and-Hold Amplifier with 38GHz Ana...

引用

10th International Conference on microwave and Millimeter Wave technology, ICMMT 2018

作者： Shen, Yu Zhang, Yi Yang, Lei Li, Xiaopeng Liu, Zhonghua Zhang, Yin Guo, Yufeng National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology Nanjing210023 China College of Electronic and Optical Engineering College of Microelectronics Nanjing University of Posts and Telecommunications Nanjing210023 China State Key Laboratory of Millimeter Waves Nanjing210096 China Post-Doctoral Research Center JiangSu HengXin Technology Co. Ltd Yixing214222 China Nanjing Electronic Devices Institute China Nanjing GuoBo Electronics Co. Ltd China

ISBN: (纸本)9781538624166

In this paper, a bipolar track-and-hold amplifier(THA), designed in a 0.13um SiGe technology is presented. A novel output buffer is proposed to enhance the hold-isolation and the bandwidth. The spurious free dynamic range (SFDR) is larger than 53.8dB for 1-3GHz input frequency with a 0.6Vpp input signal. The input bandwidth up to 38GHz is realized with a sampling rate of 10GS/s. The total DC power consumption is 586mW with a supply voltage of -5V. The layout size is 339x210 um2. As compared to the advanced silicon-based THAs, this work features high speed, low total harmonic distortion (THD), good linearity and wide bandwidth. © 2018 IEEE.

关键词： Bandwidth

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A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure

A High-Precision Delay Faults Testing Technique Based on the...

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Xiaoting Liu Xuewei Zhang Haofei Hong Guopeng Zhou Zixuan Wang Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced.

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A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution

A Wide-Range and High-Linearity Timing Generator with 1.25ps...

引用

International Conference on Integrated Circuits and microsystems (ICICM)

作者： Tianyang Chen Qianyu Wang Ze Wang Zhiwei Qi Zhenhua Han Lu Liu Shanwen Hu College of Intergrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of −20 ~ 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB.

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Multi-Instantiation Top-Level Routing Technique Based on Decision Negotiation Algorithm

Multi-Instantiation Top-Level Routing Technique Based on Dec...

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International Conference on Electronics technology (ICET)

作者： Hang Yang Xuewei Zhang Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

With the development of integrated circuit, multi-instantiated block technology is considered as a reliable optimization direction of chip design, which can effectively save the storage and labor cost in the development process, but brings new challenges to the top layer routing at the same time. On this basis, a multi-instantiation top-level routing algorithm based on decision negotiation is designed in this paper, which effectively solves the problems of multi-instantiated block routing, including long routing time and too long path length. In this paper, a non-uniform grid form is proposed to formulate alternative path sets and determine alternative routing channels between endpoints. The decision extraction and decision evaluation algorithms are used to deal with the path redundancy and short circuit problems generated by multiple instantiations. The feasible solution is determined by improved BFS (Breadth First Search) algorithm on the candidate decision set. The optimal solution with the shortest path in Manhattan is determined by iterative decision evaluation in the feasible solution. In order to verify the accuracy and effectiveness of the proposed method, a verification experiment is conducted in this paper for a number of multi-instantiation modules within 100. The experimental results show that the routing time of the proposed multi-instantiation top-level routing algorithm based on decision negotiation is between 0.1s and 3s, and the ratio of the path length to the standard value is over 95%, on the basis of a 100% success ratio.

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A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide Input Range of 4.5-35V

A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide ...

引用

International Conference on Integrated Circuits and microsystems (ICICM)

作者： Yifei Du Xin Wang Wei Wu Zhenhua Han Zhiwei Qi Zixuan Wang ShanWen Hu College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

This work presents a high-precision and wide-input-range reference voltage source based on a 180nm BCD process. The reference voltage source generates a constant voltage of 2.5V under the supply voltage ranging from 4.5V to 35V. Both a pre-regulator with current extraction, and high-order curvature compensation are proposed in this work. The current extraction circuit greatly improves the stability of output voltage, and the high-order term of V$_{\mathbf{BE}}$ in Bipolar Junction Transistor (BJT) is used for temperature compensation to achieve an output voltage with a low temperature coefficient. Simulation results show that a line regulation of 14ppm/V is achieved, and an average temperature coefficient is 1.5ppm/°C over the range of −45°C to 125°C. In addition, the Power Supply Rejection Ratio (PSRR) is 102.82dB at 10Hz.

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Multi-instantiated Block Top-layer Routing Technique Based on Steiner Tree Algorithm

Multi-instantiated Block Top-layer Routing Technique Based o...

引用

Electronics Design Automation (ISEDA), International Symposium of

作者： Hang Yang Junyuan Chen Zhikuang Cai Jingjing Guo Yufeng Guo College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing CHN National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing CHN

As the scale of chips becomes larger and larger, the time and labor cost of the overall design of a large single chip becomes higher and higher. Therefore, it has become a widely adopted solution to divide one large-scale design into several smaller blocks and realize the functions of each block respectively. In this paper, a multi-instantiated block routing technique is proposed based on the improved Steiner tree algorithm. The algorithm divides wire networks into grids and uses FLUTE to construct and decompose the minimum rectangular Steiner tree of all multipin wire networks, which will decompose any multi-pin connection into several two-pin connections. It abstracts the functions of multi-instantiated blocks involved, and adds fixed pins on the edge of them. The routing process will be conducted inside every block respectively. In order to verify the accuracy and validity of the proposed method, a series of verification experiments are carried out, which shows that the proposed multi-instantiated block routing algorithm can effectively reduce the path redundancy caused by multiple pass-throughs in blocks and improve the routing process efficiency.

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Complete Timing Model of ECSM Lookup Table for CMOS Inverter

Complete Timing Model of ECSM Lookup Table for CMOS Inverter

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Jiawei Wang Jingjing Guo Dongmin Zhao Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In the early days, engineers used non-linear delay models (NLDM) to estimate the circuit delay information. However, the accuracy of NLDM lookup table (LUT) decreases with the continuous change of the process, which makes the delay estimation become a difficult problem. Therefore, the effective current source model (ECSM) is proposed. The ECSM is a LUT composed of input transition time (T R ) and load capacitance (C L ), which can save the threshold crossing point (TCP) of the output waveform to better estimate the delay. However, the timing model is needed to reduce re-presentations, due to the high cost of building the library of ECSM. In this work, we present a timing model of the complete ECSM LUT for a CMOS inverter. The timing model is divided into two cases with a total of five regions. The proposed timing model is further analyzed by judging the value of threshold crossing points’ voltage (V TCP ) and drain to source saturation voltage (V dsat ), and the model is simplified for different threshold crossing points. Compared with the simulation results of HSPICE, the model is accurate with a maximum error of 2.35% and a maximum average error of 0.45%, which reduces the repetitive simulation of HSPICE.

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Stage Delay Calculation Method Considering Effective Capacitance

Stage Delay Calculation Method Considering Effective Capacit...

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International Conference on Electronics technology (ICET)

作者： Peiwen Zha Jingjing Guo Shugang Zhang College of Integrated Circuit Secience and Engineering National and Local Joint Engineering Laboratory of RF Intergration and Micro-assembly Technology Nanjing University of Posts and Telecommunication Nanjing China

ISBN: (数字)9798350363951

ISBN: (纸本)9798350363968

A key part of a static timing tool is its delay calculation engine-responsible for computing delay, slew, and waveform information from models of logic gates and interconnect parasitic. A stage delay calculator includes cell delay and wire delay. In previous studies, they are often independent. With the advancement of technology, the Miller effect and highly resistive load interconnect have increased the interdependency between cell and wire delay calculations. In this paper, we propose a stage delay calculation approach that utilizes effective capacitance(Ceff) to address the computation of delays and waveforms for both cells and wires. Furthermore, machine learning is employed in the calculation of wire delay, modeling the interconnects using Ceffs as a feature. Experimental results demonstrate that the proposed delay calculation method achieves an accuracy within 1.66% of the delays calculated by SPICE.

关键词： Resistance Accuracy Computational modeling Machine learning Logic gates Capacitance SPICE

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A 1-4 GHz Low Noise Amplifier in 0.5-μm E-Mode InGaAs pHEMT technology

A 1-4 GHz Low Noise Amplifier in 0.5-μm E-Mode InGaAs pHEMT...

引用

2017 7th IEEE International Symposium on microwave, Antenna, Propagation, and EMC Technologies

作者： Hairui Song Shu Yu Yufeng Guo Shanwen Hu National & Local Joint Engineering Laboratory for RF Integration and Micro-packaging Technologies College of Electronic Science and Engineering Nanjing University of Posts and Telecommunications

This paper presents a 1-4 GHz low noise amplifier（LNA） for broadband communication system. A capacitive feedback gain compensation circuit is proposed to increase the high frequency gain. The LNA exhibits a voltage gain of 20-23 d B, a noise figure of 1.8-2.3 d B during 1-4 GHz frequency *** input S11 is-13 d B10 d B and the output S22 is-18 d B10 d B. The proposed LNA is realized in 0.5-μm Gate-Length E-Mode In Ga As p HEMT Process and occupies 0.96 mm2 area. The power consumption is 250 m W with 5 V supply.

关键词： pHEMT feedback low-noise amplifier(LNA) wideband

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A 13GS/s One-Bit ADC with 18GHz Analog Bandwith Based on InP DHBT technology 14

A 13GS/s One-Bit ADC with 18GHz Analog Bandwith Based on InP...

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14th IEEE International Conference on Solid-State and Integrated Circuit technology, ICSICT 2018

作者： Li, Xiaopeng Wang, Zhigong Zhang, Yi Zhang, Youtao Zhang, Min Institute of RF - OE ICs Southeast University Nanjing210096 China Nanjing GuoBo Electronics Co. Ltd Nanjing210016 China Nanjing Electronic Devices Institute Nanjing210016 China National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology Nanjing210046 China State Key Laboratory of Millimeter Waves Southeast University Nanjing210096 China Post-Doctoral Research Center JiangSu HengXin Technology Co. Ltd Yixing214222 China Science and Technology on Monolithic Intergrated Circuits and Modules Laboratory Nanjing210016 China

ISBN: (纸本)9781538644409

In this paper, an ultra-high-speed ultra-wide-bandwidth one-bit analog-to-digital converter (ADC) is implemented. The chip uses a latched high-sensitivity comparator to achieve one-bit quantization, and an integrated 1:8 demultiplexer to reduce the data rate of the output ports, which is helpful for system applications. The chip is implemented with a 0.7μm InP DHBT process. Measurement results show that the sampling rate of the chip is up to 13GS/s, the analog input bandwidth is greater than 18GHz, the input sensitivity is less than -25dBm, and the power consumption is 1.2W. © 2018 IEEE.

关键词： Indium phosphide

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