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IEEE International Conference on Communications (ICC)

作者： Wanyue Zhang Yunchao Song Chen Liu Zheng Huang Mujun Qian College of Electronic and Optical Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

ISBN: (数字)9781728190549

ISBN: (纸本)9781728190556

This paper investigates hybrid-field channel estimation for extremely large-scale MIMO (XL-MIMO) systems. Different from the previous algorithms based on sparsity, the proposed algorithm considers both the low-rank structure and the sparsity of the channel, leading to a more accurate estimation performance. Particularly, we formulate the estimation problem of the hybrid-field channel as a sparse matrix recovery problem with a fixed-rank constraint. However, this problem encounters two challenges: the non-smooth $\ell_{1}-\mathbf{norm}$ term and the non-convex fixed-rank matrix constraint. To address these challenges, we employ the proximal operator to handle the non-smooth $\ell_{1}-\mathbf{norm}$ term and consider the set of matrices with a fixed rank as the fixed-rank matrix manifold. Then a fixed-rank matrix manifold-based proximal gradient (FRM-PG) algorithm is proposed to smoothly search the solution on the fixed-rank matrix manifold, where the descent direction is derived in each iteration. Simulation results demonstrate that the proposed algorithm outperforms the classical channel estimation algorithms.

关键词： Manifolds Accuracy Simulation Channel estimation Estimation Sparse matrices Optimization

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Stage Delay Calculation Method Considering Effective Capacitance

Stage Delay Calculation Method Considering Effective Capacit...

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International Conference on Electronics technology (ICET)

作者： Peiwen Zha Jingjing Guo Shugang Zhang College of Integrated Circuit Secience and Engineering National and Local Joint Engineering Laboratory of RF Intergration and Micro-assembly Technology Nanjing University of Posts and Telecommunication Nanjing China

ISBN: (数字)9798350363951

ISBN: (纸本)9798350363968

A key part of a static timing tool is its delay calculation engine-responsible for computing delay, slew, and waveform information from models of logic gates and interconnect parasitic. A stage delay calculator includes cell delay and wire delay. In previous studies, they are often independent. With the advancement of technology, the Miller effect and highly resistive load interconnect have increased the interdependency between cell and wire delay calculations. In this paper, we propose a stage delay calculation approach that utilizes effective capacitance(Ceff) to address the computation of delays and waveforms for both cells and wires. Furthermore, machine learning is employed in the calculation of wire delay, modeling the interconnects using Ceffs as a feature. Experimental results demonstrate that the proposed delay calculation method achieves an accuracy within 1.66% of the delays calculated by SPICE.

关键词： Resistance Accuracy Computational modeling Machine learning Logic gates Capacitance SPICE

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Circularly polarized leaky wave antenna based on compound left-right-hand structure 13

Circularly polarized leaky wave antenna based on compound le...

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13th International Conference on microwave and Millimeter Wave technology, ICMMT 2021

作者： Yin, Huanyu Li, Pinyan Liu, Leilei National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology College of Electronic and Optical Engineering Nanjing University of Posts and Telecommunications Nanjing210003 China

ISBN: (纸本)9781665434379

In this paper, a circularly polarized leaky wave antenna based on compound left-right-hand structure (CRLH) is proposed. In this design, the equivalent series capacitance is realized by the annular groove on the metal microstrip, and the parallel inductance is realized by the metal through hole. The antenna can realize frequency beam scanning in 14-18GHz and circular polarization in 15.5-18GHz. © 2021 IEEE.

关键词： Traveling wave antennas

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Tradeoff Between the Breakdown Voltage and Specific On-Resistance of SOI RESUrf LDMOS

Tradeoff Between the Breakdown Voltage and Specific On-Resis...

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International Conference on ASIC

作者： Yufeng Guo Kemeng Yang Jing Chen Man Li Zhengfei Jiang Jiafei Yao Jun Zhang Maolin Zhang College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing China

The tradeoff between the breakdown voltage (BV) and specific on-resistance (R on,sp ) is an important issue for the power device. Baliga’s Figure of Merits (BFOM) and silicon limit both are useful tools to evaluate this relationship. However, the strong 2-D effect is not considered in the conventional BFOM and the present silicon limit. In this paper, a new BFOM model of SOI RESUrf LDMOS is proposed based on the formulized 2-D electric field in the drift region. Then, the device structure parameters are optimized to maximize the BFOM. A novel silicon limit and critical electric field are also derived. The differences between the lateral and the vertical devices are investigated and compared. The mechanism is discussed. The simulation based on the TCAD tool is employed to verify the novel BFOM and silicon limit.

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High responsivity and fast response 8×8β-Ga_(2)O_(3)solar-blind ultraviolet imaging photodetector array

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Science China(Technological Sciences) 2023年第11期66卷 3259-3266页

作者： SHEN GaoHui LIU Zeng TANG Kai SHA ShuLin LI Lei TAN Chee-Keong GUO YuFeng TANG WeiHua Innovation Center of Gallium Oxide Semiconductor(IC-GAO) College of Integrated Circuit Science and EngineeringNanjing University of Posts and TelecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory for RF Integration and Micro-Assembly Technologies Nanjing University of Posts and TelecommunicationsNanjing 210023China Key Laboratory of Aerospace Information Materials and Physics(NUAA) MIITNanjing 211106China College of Physics MIIT Key Laboratory of Aerospace Information Materials and PhysicsKey Laboratory for Intelligent Nano Materials and DevicesNanjing University of Aeronautics and AstronauticsNanjing 211106China Advanced Materials Thrust Function HubThe Hong Kong University of Science and Technology(Guangzhou)Nansha 511458China Department of Electronic and Computer Engineering School of EngineeringThe Hong Kong University of Science and TechnologyHong Kong 999077China

In this work,an 8×8 Ga_(2)O_(3)solar-blind ultraviolet photodetector array is introduced for image sensing *** 2-in wafer-scaled Ga_(2)O_(3)thin film was grown by metalorganic chemical vapor deposition technique;and the photodetector array was fabricated through ultraviolet photolithography,lift-off,and electron-beam *** addition to the high solar-blind/visible rejection ratio of 104,every photodetector cell in the array has high performance and fast response speed,such as responsivity of 49.4 A W^(-1),specific detectivity of 6.8×10^(14)Jones,external quantum efficiency of 1.9×10^(4)%,linear dynamic range of 117.8 d B,and response time of 41 ms,respectively,indicating the high photo-response performance of the ***,the photodetector array displayed uniform responsivity with a standard deviation of~6%,and presented a sensing image of low chromatic aberration,owing to the high resolution of the photodetector *** a word,this work may contribute to developing Ga_(2)O_(3)-based optoelectronic device applications.

关键词： Ga_(2)O_(3) photodetector array imaging photo-response

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α-Ga₂O₃ Photodetector With Responsivity Over A/W Level Based on Sn-Assisted Mist-CVD

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IEEE Sensors Journal 2024年第2期25卷 2518-2524页

作者： Gang Li Haoxuan Peng Yingxu Wang Suhao Yao Maolin Zhang Yufeng Guo Weihua Tang Innovation Center for Gallium Oxide Semiconductor (IC-GAO) College of Integrated Circuit Science and Engineering and the National and Local Joint Engineering Laboratory for RF Integration and Micro-Assembly Technologies Nanjing University of Posts and Telecommunications Nanjing China College of Electrical and Electronic Engineering Wenzhou University Wenzhou China

In recent years, $\alpha $ -Ga2O3 and $\alpha $ -Ga2O3-based photodetectors (PDs) have garnered significant attention due to their unique advantages in deep-ultraviolet (DUV) photodetection. However, the growth of $\alpha $ -Ga2O3 thin films via the mist chemical vapor deposition (mist-CVD) method faces several challenges, such as inferior crystallization quality, which impedes the development of high-performance PDs. In this study, we successfully achieved high-quality $\alpha $ -Ga2O3 epitaxy on the $\alpha $ -Al2O3 substrate using the tin (Sn)-assisted mist-CVD technique. A DUV PD was subsequently fabricated on the epitaxial film, and its detection performance was thoroughly evaluated. The PD achieved a photocurrent of up to 175.40 nA and a signal-to-noise ratio (SNR) of 76.5 dB. Most notably, it also exhibited a high responsivity of up to 3.76 A/W, an external quantum efficiency (EQE) of 1841.12%, and a detectivity of $1.8\times 10^{{11}}$ Jones, underscoring the potential of the Sn-assisted mist-CVD method for advancing the development of next-generation $\alpha $ -Ga2O3 DUV PDs.

关键词： Epitaxial growth Gallium Sensors Photodetectors Substrates Scanning electron microscopy Photonic band gap X-ray scattering Transmission electron microscopy Tin

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Sic-on-Insulator Based Lateral Power Device and it' S Analytical Models

SSRN

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SSRN 2024年

作者： Yao, Jiafei Li, Ang Liu, Yuao Hu, Ziwei Li, Man Yang, Kemeng Zhang, Jun Chen, Jing Zhang, Maolin Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly technology Nanjing China Nantong Institute of Nanjing University of Posts and Telecommunications Nantong China

This paper proposes the concept of SiC-on-insulator (SiCOI) lateral power device and its analytical models. The SiCOI technology provides the dielectric isolation and improves the vertical breakdown. The analytical models provide the physic insight of the surface potential and electric field distributions for both full and partial depletion cases. The optimal breakdown voltage and doping concentration are deduced to analysis the breakdown mechanism qualitatively. The specific on-resistance in the drift region was also calculated to analysis the conduction characteristics. The influences of the structure parameters on the performances of the SiCOI lateral power device are investigated by the analytical model and numerical simulation. The analytical results of the proposed model are well agreement with the numerical results, confirming the validity of the proposed unified analytical model. Both of the analytical and numerical results provide the physic explanation and effective solution for optimizing the electric field and improving breakdown voltage for the SiCOI lateral power device. © 2024, The Authors. All rights reserved.

关键词： Electric breakdown

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Double Dielectrics Enhancement on the Ldmos Using High-K Field Dielectric and Low-K Buried Dielectric

SSRN

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SSRN 2022年

作者： Yao, Jiafei Liu, Xin Sun, Mingshun Xu, Tianci Li, Man Chen, Jing Zhang, Maolin Zhang, Jun Guo, Yufeng Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing China

This paper investigates the double dielectrics enhancement LDMOS (DDE LDMOS) with high-k field dielectric and low-k buried dielectric. The analytical models of the potential and electric field, optimal breakdown voltage and drift doping concentration are established for this novel LDMOS. The validity of the analytical models is confirmed by the simulation results. Based on the analytical and simulate results, the modulation mechanism of the high-k field dielectric and low-k buried dielectric on the electric field and breakdown characteristics of DDE LDMOS are analyzed and compared. Compared to the conventional LDMOS, the specific on-resistance of DDE LDMOS is reduced by 19%, the breakdown voltage and figure of merit ( FOM ) of the DDE LDMOS can be improved by 62% and 222.4% when the permittivity of high-k field dielectric and low-k buried dielectric are 100 and 2. Meanwhile, the transfer characteristic, output characteristic, frequency characteristic and switching characteristic of the DDE LDMOS are also discussed. © 2022, The Authors. All rights reserved.

关键词： MOS devices

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A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure

A High-Precision Delay Faults Testing Technique Based on the...

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Xiaoting Liu Xuewei Zhang Haofei Hong Guopeng Zhou Zixuan Wang Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced.

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A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution

A Wide-Range and High-Linearity Timing Generator with 1.25ps...

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Tianyang Chen Qianyu Wang Ze Wang Zhiwei Qi Zhenhua Han Lu Liu Shanwen Hu College of Intergrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of −20 ~ 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB.

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