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13th International Conference on microwave and Millimeter Wave Technology, ICMMT 2021

作者： Yi, Yao Zhang, Yerong Nanjing University Of Posts And Telecommunications National And Local Joint Engineering Laboratory Of RF Integration And Microassembly Tchnology Nanjing210023 China

ISBN: (纸本)9781665434379

This paper presents a substrate integrated waveguide (SIW) bandpass filter with switchable center frequency and bandwidth (BW). PIN diodes are used to control the on-off between the via posts and the ground or to change the length of the slot line. When the via posts located in the middle of the resonator is grounded, the electric field is disturbed and the frequency rises. When the column at the coupling window is grounded, the coupling quantity decreases and the bandwidth also decreases. Thus the BWs and frequencies can be switched in the same filter. The SIW filter has three center frequencies that can be switched: 2.62 GHz, 2.86 GHz and 3.10 GHz. And there are two switchable BWs for each center frequency. Return loss is better than 13 dB and insertion loss range from 1.58 dB to 2.25 dB. © 2021 IEEE.

关键词： Bandwidth

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A Compact Dual-Band Radiator-Shared Antenna With Enhanced Isolation and Flexible Frequency Ratio Regulation

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IEEE Transactions on Antennas and Propagation 2025年

作者： Wang, Wenlei Jin, Huayan Yu, Weiliang Liu, Leilei Luo, Guo Qing Hangzhou Dianzi University Key Laboratory of RF Circuits System of Ministry of Education School of Electronics and Information Xiasha High Education Zone Hangzhou310018 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration College of Electronic and Optical Engineering Nanjing210003 China

In this article, a radiator-shared duplex antenna (RSDA) with enhanced isolation, flexible frequency ratio regulation, and compact size is proposed for applications in multiband/standard communication systems. The radiator-shared design is based on a shaping scheme by utilizing a parasitic resonator to make the lower-band and higher-band antennas have the same radiation structure. Customized feeding methods are employed to individually excite the high-order substrate integrated waveguide (SIW) cavity mode and the fractional-order patch mode, enabling dual-band operation and allowing a flexible frequency ratio regulation from 1.3 to 1.7. The proposed RSDA eliminates the need for decoupling structures or additional duplexing/filtering circuits. Isolation enhancement of over 24 dB is accomplished by exploiting the layered feeding architecture, shielded sidewalls, and a high-pass SIW feedline to suppress the feedline coupling, surface wave interference, and out-of-band signal propagation, respectively. For verification, a prototype of the proposed RSDA was measured, demonstrating dual-wideband operation that encompasses the targeted 5G/Sub 6G n78 band (3.3–3.6 GHz) and n79 band (4.8–5 GHz). The prototype achieved a peak gain of 5.3 dBi at 3.45 GHz and 7.4 dBi at 4.95 GHz, while exhibiting a high isolation level exceeding 53 dB and good radiation patterns. © 1963-2012 IEEE.

关键词： Substrate integrated waveguides

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Low-Profile Independent Dual Linear Polarization Reflectarray Filtenna

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IEEE Antennas and Wireless Propagation Letters 2025年第6期24卷 1372-1376页

作者： Yu, Weiliang Tong, Shijun Wang, Wenlei Dai, Xiwang Liu, Leilei Luo, Guo Qing Hangzhou Dianzi University Xiasha High Education Park Key Laboratory of RF Circuits & System Ministry of Education School of Electronics and Information Hangzhou310018 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration College of Electronic and Optical Engineering Nanjing210003 China

This paper proposes a low-profile dual-linear polarization reflectarray filtenna with a unit cell featuring a dual-polarization magneto-electric (ME) dipole based on split-ring resonators (SRRs). The ME dipole has two independent feeding sections, each connected to a separate open-ended microstrip line, enabling independent control of dual-polarization reflection phases. The ME dipole and SRRs generate low and high frequency radiation nulls, respectively. The filtenna achieves 3dB gain bandwidths of 19.3% for x-polarization and 18.5% for y-polarization, with maximum gains of 21.77dBi (35.1% efficiency) for x-polarization and 21.93dBi (36.4% efficiency) for y-polarization. The selectivity characteristics for x- and y-polarizations are 0.5 and 0.52, respectively. With a relative thickness of only 0.072λ, this filtenna is suitable for long-distance communication systems requiring high-capacity data transmission and integration. © 2002-2011 IEEE.

关键词： Reflection

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Fully Shielded Half-Mode SIW Cavity-Based Compact Filtenna For 5G n257 Operations

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IEEE Antennas and Wireless Propagation Letters 2025年

作者： Wang, Wenlei Jin, Huayan Yu, Weiliang Liu, Leilei Luo, Guo Qing Hangzhou Dianzi University Key Laboratory of RF Circuits & System of Ministry of Education School of Electronics and Information Xiasha High Education Zone Hangzhou310018 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration College of Electronic and Optical Engineering Nanjing210003 China

A compact filtenna is presented in this letter based on the study on a fully shielded half-mode substrate-integrated waveguide (FSD-HMSIW) cavity. The proposed FSD-HMSIW cavity uses a shielded combined boundary instead of the open magnetic boundary, enabling radiation while preventing energy leakage into the substrate region. Resultantly, two FSD-HMSIW cavities can be closely placed to reduce the size and produce two in-band resonance poles, as well as an additional radiation null due to the electric-dominated cross coupling. By further adding a shorted concave loop, a magnetic-dominated cross coupling path can be introduced to produce a resonance pole and an extra radiation null at the lower band. The active simulation of a 1 × 8 beam scanning array verifies that the proposed compact filtenna can provide a stable bandpass filtering response over a wide beam-scanning angle of ±45°. For verification, a prototype of the proposed filtenna with a compact size of 0.32λ0 × 0.32λ0 was fabricated and tested, showing a wide bandwidth covering the 5G n257 band (26.5–29.5 GHz), a high peak gain of 6.8 dBi, excellent frequency selectivity, and good radiation patterns. © 2002-2011 IEEE.

关键词： Filtenna fully shielded cavity millimeter-wave (mmW) miniaturization wide scanning angle

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Sic-on-Insulator Based Lateral Power Device and it' S Analytical Models

SSRN

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SSRN 2024年

作者： Yao, Jiafei Li, Ang Liu, Yuao Hu, Ziwei Li, Man Yang, Kemeng Zhang, Jun Chen, Jing Zhang, Maolin Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly technology Nanjing China Nantong Institute of Nanjing University of Posts and Telecommunications Nantong China

This paper proposes the concept of SiC-on-insulator (SiCOI) lateral power device and its analytical models. The SiCOI technology provides the dielectric isolation and improves the vertical breakdown. The analytical models provide the physic insight of the surface potential and electric field distributions for both full and partial depletion cases. The optimal breakdown voltage and doping concentration are deduced to analysis the breakdown mechanism qualitatively. The specific on-resistance in the drift region was also calculated to analysis the conduction characteristics. The influences of the structure parameters on the performances of the SiCOI lateral power device are investigated by the analytical model and numerical simulation. The analytical results of the proposed model are well agreement with the numerical results, confirming the validity of the proposed unified analytical model. Both of the analytical and numerical results provide the physic explanation and effective solution for optimizing the electric field and improving breakdown voltage for the SiCOI lateral power device. © 2024, The Authors. All rights reserved.

关键词： Electric breakdown

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A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution

A Wide-Range and High-Linearity Timing Generator with 1.25ps...

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Tianyang Chen Qianyu Wang Ze Wang Zhiwei Qi Zhenhua Han Lu Liu Shanwen Hu College of Intergrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of −20 ~ 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB.

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A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure

A High-Precision Delay Faults Testing Technique Based on the...

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Xiaoting Liu Xuewei Zhang Haofei Hong Guopeng Zhou Zixuan Wang Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced.

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Multi-Instantiation Top-Level Routing Technique Based on Decision Negotiation Algorithm

Multi-Instantiation Top-Level Routing Technique Based on Dec...

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International Conference on Electronics Technology (ICET)

作者： Hang Yang Xuewei Zhang Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

With the development of integrated circuit, multi-instantiated block technology is considered as a reliable optimization direction of chip design, which can effectively save the storage and labor cost in the development process, but brings new challenges to the top layer routing at the same time. On this basis, a multi-instantiation top-level routing algorithm based on decision negotiation is designed in this paper, which effectively solves the problems of multi-instantiated block routing, including long routing time and too long path length. In this paper, a non-uniform grid form is proposed to formulate alternative path sets and determine alternative routing channels between endpoints. The decision extraction and decision evaluation algorithms are used to deal with the path redundancy and short circuit problems generated by multiple instantiations. The feasible solution is determined by improved BFS (Breadth First Search) algorithm on the candidate decision set. The optimal solution with the shortest path in Manhattan is determined by iterative decision evaluation in the feasible solution. In order to verify the accuracy and effectiveness of the proposed method, a verification experiment is conducted in this paper for a number of multi-instantiation modules within 100. The experimental results show that the routing time of the proposed multi-instantiation top-level routing algorithm based on decision negotiation is between 0.1s and 3s, and the ratio of the path length to the standard value is over 95%, on the basis of a 100% success ratio.

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Multi-instantiated Block Top-layer Routing Technique Based on Steiner Tree Algorithm

Multi-instantiated Block Top-layer Routing Technique Based o...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Hang Yang Junyuan Chen Zhikuang Cai Jingjing Guo Yufeng Guo College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing CHN National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing CHN

As the scale of chips becomes larger and larger, the time and labor cost of the overall design of a large single chip becomes higher and higher. Therefore, it has become a widely adopted solution to divide one large-scale design into several smaller blocks and realize the functions of each block respectively. In this paper, a multi-instantiated block routing technique is proposed based on the improved Steiner tree algorithm. The algorithm divides wire networks into grids and uses FLUTE to construct and decompose the minimum rectangular Steiner tree of all multipin wire networks, which will decompose any multi-pin connection into several two-pin connections. It abstracts the functions of multi-instantiated blocks involved, and adds fixed pins on the edge of them. The routing process will be conducted inside every block respectively. In order to verify the accuracy and validity of the proposed method, a series of verification experiments are carried out, which shows that the proposed multi-instantiated block routing algorithm can effectively reduce the path redundancy caused by multiple pass-throughs in blocks and improve the routing process efficiency.

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Complete Timing Model of ECSM Lookup Table for CMOS Inverter

Complete Timing Model of ECSM Lookup Table for CMOS Inverter

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International Conference on Integrated Circuits and microsystems (ICICM)

作者： Jiawei Wang Jingjing Guo Dongmin Zhao Zhikuang Cai College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing China

In the early days, engineers used non-linear delay models (NLDM) to estimate the circuit delay information. However, the accuracy of NLDM lookup table (LUT) decreases with the continuous change of the process, which makes the delay estimation become a difficult problem. Therefore, the effective current source model (ECSM) is proposed. The ECSM is a LUT composed of input transition time (T R ) and load capacitance (C L ), which can save the threshold crossing point (TCP) of the output waveform to better estimate the delay. However, the timing model is needed to reduce re-presentations, due to the high cost of building the library of ECSM. In this work, we present a timing model of the complete ECSM LUT for a CMOS inverter. The timing model is divided into two cases with a total of five regions. The proposed timing model is further analyzed by judging the value of threshold crossing points’ voltage (V TCP ) and drain to source saturation voltage (V dsat ), and the model is simplified for different threshold crossing points. Compared with the simulation results of HSPICE, the model is accurate with a maximum error of 2.35% and a maximum average error of 0.45%, which reduces the repetitive simulation of HSPICE.

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