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Design of High Performance MXene/Oxide Structure Memristors for Image Recognition Applications

Chinese Journal of Electronics 2024年第2期33卷 336-345页

作者： Xiaojuan LIAN Yuelin SHI Xinyi SHEN Xiang WAN Zhikuang CAI Lei WANG The College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications The National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications

Recent popularity to realize image recognition by memristor-based neural network hardware systems has been witnessed owing to their similarities to neurons and ***,the stochastic formation of conductive filaments inside the oxide memristor devices inevitably makes them face some drawbacks,represented by relatively higher power consumption and severer resistance switching *** this work,we design and fabricate the Ag/MXene（Ti3C2）/SiO2/Pt memristor after considering the stronger interactions between Ti3C2and Ag ions,which lead to a Ti3C2/SiO2structure memristor owning to much lower "SET" voltage and smaller resistance switching fluctuation than pure ***,the conductances of the Ag/Ti3C2/SiO2/Pt memristor have been modulated by changing the number of the applied programming pulse,and two typical biological behaviors,i.e.,longterm potentiation and long-term depression,have been ***,device conductances are introduced into an integrated device-to-algorithm framework as synaptic weights,by which the MNIST hand-written digits are recognized with accuracy up to 77.39%.

关键词： Memristor MXene/Oxide structure Electrical characteristics First-principles calculations Image recognition

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High-performance artificial neurons based on Ag/MXene/GST/Pt threshold switching memristors

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Chinese Physics B 2023年第1期32卷 458-463页

作者：连晓娟付金科高志瑄顾世浦王磊 The College of Integrated Circuit Science and Engineering Nanjing University of Posts and TelecommunicationsNanjing 210023China The National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and TelecommunicationsNanjing 210023China

Threshold switching(TS) memristors can be used as artificial neurons in neuromorphic systems due to their continuous conductance modulation, scalable and energy-efficient properties. In this paper, we propose a low power artificial neuron based on the Ag/MXene/GST/Pt device with excellent TS characteristics, including a low set voltage(0.38 V)and current(200 nA), an extremely steep slope(< 0.1 m V/dec), and a relatively large off/on ratio(> 10^(3)). Besides, the characteristics of integrate and fire neurons that are indispensable for spiking neural networks have been experimentally demonstrated. Finally, its memristive mechanism is interpreted through the first-principles calculation depending on the electrochemical metallization effect.

关键词： memristors artificial neurons 2D MXene Ge_(2)Sb_(2)Te_(5)

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Study of the influence of virtual guard ring width on the performance of SPAD detectors in 180 nm standard CMOS technology

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Journal of Semiconductors 2023年第11期44卷 83-88页

作者： Danlu Liu Ming Li Tang Xu Jie Dong Yuming Fang Yue Xu College of Integrated Circuit Science and Engineering Nanjing University of Posts and TelecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory of RF Integration&Micro-Assembly Technology Nanjing 210023China

The influence of the virtual guard ring width(GRW)on the performance of the p-well/deep n-well single-photon avalanche diode(SPAD)in a 180 nm standard CMOS process was *** simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1μ*** is experimentally found that,compared with an SPAD with GRW=2μm,the dark count rate(DCR)and afterpulsing probability(AP)of the SPAD with GRW=1μm is significantly increased by 2.7 times and twofold,respectively,meanwhile,its photon detection probability(PDP)is saturated and hard to be promoted at over 2 V excess bias *** the fill factor(FF)can be enlarged by reducing GRW,the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling(TAT)effect in the 1μm guard ring *** comparison,the SPAD with GRW=2μm can achieve a better trade-off between the FF and noise *** study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.

关键词： single-photon avalanche diode(SPAD) virtual guard ring dark count rate(DCR) photon detection probability(PDP) afterpulsing probability(AP)

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Review of the SiC LDMOS power device

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Journal of Semiconductors 2024年第8期45卷 4-17页

作者： Ziwei Hu Jiafei Yao Ang Li Qi Sun Man Li Kemeng Yang Jun Zhang Jing Chen Maolin Zhang Yufeng Guo College of Integrated Circuit Science and Engineering(Industry-Education Integration School) Nanjing University of Posts andT elecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing 210023China Nantong Institute of Nanjing University of Posts and Telecommunications Nantong 226000China

Silicon carbide(SiC),as a third-generation semiconductor material,possesses exceptional material properties that significantly enhance the performance of power *** SiC lateral double-diffused metal–oxide–semiconductor(LDMOS)power devices have undergone continuous optimization,resulting in an increase in breakdown voltage(BV)and ultra-low specific on-resistance(Ron,sp).This paper has summarized the structural optimizations and experimental progress of SiC LDMOS power devices,including the trench-gate technology,reduced surface field(RESUrf)technology,doping technology,junction termination techniques and so *** paper is aimed at enhancing the understanding of the operational mechanisms and providing guidelines for the further development of SiC LDMOS power devices.

关键词： SiC LDMOS specific on-resistance breakdown voltage

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An Active Gate Driver with Controllable Gate Current for SiC MOSFETs 9

An Active Gate Driver with Controllable Gate Current for SiC...

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9th International Conference on Integrated Circuits and microsystems, ICICM 2024

作者： Jiang, Zhengfei Yao, Jiafei Dai, Yuxuan Hu, Ziwei Li, Man Zhang, Yi Wang, Zixuan Cai, Zhikuang Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798331509453

An active gate driver (AGD) with controllable gate current (CGC) for SiC MOSFETs is proposed to reduce voltage overshoots and current overshoots. In the CGC-AGD, the controllable current overshoot suppression circuit and voltage overshoot suppression circuit are designed to control the rate of changes in current (di/dt) and voltage (dv/dt) to effectively reduce overshoots. Meanwhile, the current conversion circuit and the push-pull amplifier circuit compensate for the current reduction resulting from the overshoot suppression. This paper simulated the current and voltage overshoot during the switching process based on a double pulse test set up with a 1200V SiC MOSFET by LTspice software. The simulation results show that the current overshoot was reduced by 60% and the voltage overshoot was reduced by 22% when compared to the conventional gate driver (CGD). While compared with the AGD circuit, the current overshoot of CGC-AGD is reduced by 26% and the voltage overshoot is reduced by 19%. These results demonstrate that the CGC-AGD has better suppress on current and voltage overshoot. © 2024 IEEE.

关键词： MOSFET devices

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A Scalable Model for On-Chip Interdigital Capacitor Based on Space-Mapping Neural Network 9

A Scalable Model for On-Chip Interdigital Capacitor Based on...

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9th International Conference on Integrated Circuits and microsystems, ICICM 2024

作者： Xiong, Yuqing Guo, Siqing Hu, Shanwen Gu, Yan Fang, Yuming Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory RF Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798331509453

A scalable model for on-chip interdigital capacitor is proposed based on space-mapping neural network (SMNN), which combines the equivalent circuit of capacitor and perceptron neural network. By expanding the traditional series equivalent circuit into a π-type structure and adding a series network of resistor and capacitor to characterize the coupling effect, the variation of the equivalent series resistance (ESR) and S-parameter with frequency can be effectively predicted. According to the mathematical equation, the value of each component for the 1-π equivalent circuit model can be quickly and correctly obtained. In order to effectively improve the prediction accuracy and convergence speed of neural network, Particle Swarm Optimization (PSO) and Levenberg-Marquardt Back Propagation (LMBP) are used to select and optimize the weights and thresholds of the neural networks. Compared with the traditional neural network model, the proposed SMNN reduces the number of neurons required to map the input-output nonlinear relationship, so that the modeling time is only reduced to 10 ∼ 15 seconds, and the test data accuracy is good. © 2024 IEEE.

关键词： Particle swarm optimization (PSO)

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A Review of Intelligent Design for Test Based on Machine Learning

A Review of Intelligent Design for Test Based on Machine Lea...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Zhao, Zeyu Cai, Zhikuang Technology College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Nanjing China

ISBN: (纸本)9798350304510

In recent years, with the development of post-Moore era, integrated circuit architecture is complex and test cost is increasing. How to apply efficient, reliable, fast and sustainable ideas to integrated circuit design has become a research hotspot in this field. Machine Learning, by virtue of its ability to quickly process abundant data information, shines in the field of Design For Test, which aims to improve the reliability of integrated circuit products and reduce design costs. In this paper, we introduce the application of Machine Learning in scan compression, Automatic Test Pattern Generation algorithm, the Test Pattern Generator in Built-In-Self-Test and test power. In addition, we prospect the foreground application of Machine Learning application in scan test, Automatic Test Pattern Generation, Built-In-Self-Test and test power. © 2023 IEEE.

关键词： Machine learning

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Tradeoff between the Breakdown Voltage and Specific On-Resistance of SOI RESUrf LDMOS 15

Tradeoff between the Breakdown Voltage and Specific On-Resis...

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15th IEEE International Conference on ASIC, ASICON 2023

作者： Guo, Yufeng Yang, Kemeng Chen, Jing Li, Man Jiang, Zhengfei Yao, Jiafei Zhang, Jun Zhang, Maolin Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210023 China

ISBN: (纸本)9798350312980

The tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp) is an important issue for the power device. Baliga's Figure of Merits (BFOM) and silicon limit both are useful tools to evaluate this relationship. However, the strong 2-D effect is not considered in the conventional BFOM and the present silicon limit. In this paper, a new BFOM model of SOI RESUrf LDMOS is proposed based on the formulized 2-D electric field in the drift region. Then, the device structure parameters are optimized to maximize the BFOM. A novel silicon limit and critical electric field are also derived. The differences between the lateral and the vertical devices are investigated and compared. The mechanism is discussed. The simulation based on the TCAD tool is employed to verify the novel BFOM and silicon limit. © 2023 IEEE.

关键词： BFOM Breakdown voltage LDMOS RESUrf Silicon limit SOI Specific on-resistance

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Stage Delay Calculation Method Considering Effective Capacitance

Stage Delay Calculation Method Considering Effective Capacit...

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7th International Conference on Electronics technology, ICET 2024

作者： Zha, Peiwen Guo, Jingjing Zhang, Shugang Nanjing University of Posts and Telecommunication National and Local Joint Engineering Laboratory of Rf Intergration and Micro-assembly Technology College of Integrated Circuit Secience and Engineering Nanjing China

ISBN: (纸本)9798350363951

A key part of a static timing tool is its delay calculation engine-responsible for computing delay, slew, and waveform information from models of logic gates and interconnect parasitic. A stage delay calculator includes cell delay and wire delay. In previous studies, they are often independent. With the advancement of technology, the Miller effect and highly resistive load interconnect have increased the interdependency between cell and wire delay calculations. In this paper, we propose a stage delay calculation approach that utilizes effective capacitance(Ceff) to address the computation of delays and waveforms for both cells and wires. Furthermore, machine learning is employed in the calculation of wire delay, modeling the interconnects using Ceffs as a feature. Experimental results demonstrate that the proposed delay calculation method achieves an accuracy within 1.66% of the delays calculated by SPICE. © 2024 IEEE.

关键词： SPICE

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Complete Timing Model of ECSM Lookup Table for CMOS Inverter 8

Complete Timing Model of ECSM Lookup Table for CMOS Inverter

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Wang, Jiawei Guo, Jingjing Zhao, Dongmin Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

In the early days, engineers used non-linear delay models (NLDM) to estimate the circuit delay information. However, the accuracy of NLDM lookup table (LUT) decreases with the continuous change of the process, which makes the delay estimation become a difficult problem. Therefore, the effective current source model (ECSM) is proposed. The ECSM is a LUT composed of input transition time (TR) and load capacitance (CL), which can save the threshold crossing point (TCP) of the output waveform to better estimate the delay. However, the timing model is needed to reduce re-presentations, due to the high cost of building the library of ECSM. In this work, we present a timing model of the complete ECSM LUT for a CMOS inverter. The timing model is divided into two cases with a total of five regions. The proposed timing model is further analyzed by judging the value of threshold crossing points' voltage (VTCP) and drain to source saturation voltage (Vdsat), and the model is simplified for different threshold crossing points. Compared with the simulation results of HSPICE, the model is accurate with a maximum error of 2.35% and a maximum average error of 0.45%, which reduces the repetitive simulation of HSPICE. © 2023 IEEE.

关键词： Table lookup

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