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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Du, Yifei Wang, Xin Wu, Wei Han, Zhenhua Qi, Zhiwei Wang, Zixuan Hu, ShanWen Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

This work presents a high-precision and wide-input-range reference voltage source based on a 180nm BCD process. The reference voltage source generates a constant voltage of 2.5V under the supply voltage ranging from 4.5V to 35V. Both a pre-regulator with current extraction, and high-order curvature compensation are proposed in this work. The current extraction circuit greatly improves the stability of output voltage, and the high-order term of VBE in Bipolar Junction Transistor (BJT) is used for temperature compensation to achieve an output voltage with a low temperature coefficient. Simulation results show that a line regulation of 14ppm/V is achieved, and an average temperature coefficient is 1.5ppm/°C over the range of -45°C to 125°C. In addition, the Power Supply Rejection Ratio (PSRR) is 102.82dB at 10Hz. © 2023 IEEE.

关键词： Temperature

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A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution 8

A Wide-Range and High-Linearity Timing Generator with 1.25ps...

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Chen, Tianyang Wang, Qianyu Wang, Ze Qi, Zhiwei Han, Zhenhua Liu, Lu Hu, Shanwen Nanjing University of Posts and Telecommunications College of Intergrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of -20 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB. © 2023 IEEE.

关键词： Phase locked loops

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A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure 8

A High-Precision Delay Faults Testing Technique Based on the...

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8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Liu, Xiaoting Zhang, Xuewei Hong, Haofei Zhou, Guopeng Wang, Zixuan Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced. © 2023 IEEE.

关键词： Frequency converters

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Wide Stopband Substrate Integrated Waveguide Filter Using Bisection and Trisection Coupling in Multilayer

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Chinese Journal of Electronics 2024年第2期33卷 436-442页

作者： Peng CHU Jianguo FENG Peng ZHU Lei GUO Long ZHANG Leilei LIU Guoqing LUO Ke WU College of Electronic and Optical Engineering Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology School of Information and Communication Engineering Dalian University of Technology Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-sen University College of Electronics and Information Engineering Shenzhen University School of Electronics and Information Hangzhou Dianzi University Poly-Grames Research Center Polytechnique Montreal

This article presents a highly efficient method for substrate-integrated-waveguide（SIW） filters to achieve very wide stopbands. By employing the proposed trisection slots in addition to the bisection slots as the inter-coupling structures, all spurious modes below TE505 of a SIW filter working in the fundamental mode TE101（f0）can be eliminated without requiring additional structure or complex theoretical analysis, without affecting the design of the fundamental passbands, and without degrading the performance of the filters. For verification, two prototype filters are designed, fabricated, and measured with wide stopbands up to 4.15f0 and 4.83f0, respectively. The proposed technique could facilitate the development of high-performance wide-stopband SIW filters for microwave/wireless circuits and systems.

关键词： Bandpass filter Wide stopband Substrate integrated waveguide Spurious mode suppression Multilayer

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Multi-instantiated Block Top-layer Routing Technique Based on Steiner Tree Algorithm

Multi-instantiated Block Top-layer Routing Technique Based o...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Yang, Hang Chen, Junyuan Cai, Zhikuang Guo, Jingjing Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing210003 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210003 China

ISBN: (纸本)9798350304510

As the scale of chips becomes larger and larger, the time and labor cost of the overall design of a large single chip becomes higher and higher. Therefore, it has become a widely adopted solution to divide one large-scale design into several smaller blocks and realize the functions of each block respectively. In this paper, a multi-instantiated block routing technique is proposed based on the improved Steiner tree algorithm. The algorithm divides wire networks into grids and uses FLUTE to construct and decompose the minimum rectangular Steiner tree of all multipin wire networks, which will decompose any multi-pin connection into several two-pin connections. It abstracts the functions of multi-instantiated blocks involved, and adds fixed pins on the edge of them. The routing process will be conducted inside every block respectively. In order to verify the accuracy and validity of the proposed method, a series of verification experiments are carried out, which shows that the proposed multi-instantiated block routing algorithm can effectively reduce the path redundancy caused by multiple pass-throughs in blocks and improve the routing process efficiency. © 2023 IEEE.

关键词： Routing algorithms

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Multi-Instantiation Top-Level Routing Technique Based on Decision Negotiation Algorithm 6

Multi-Instantiation Top-Level Routing Technique Based on Dec...

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6th International Conference on Electronics technology, ICET 2023

作者： Yang, Hang Zhang, Xuewei Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing210003 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing210003 China

ISBN: (纸本)9798350337693

With the development of integrated circuit, multi-instantiated block technology is considered as a reliable optimization direction of chip design, which can effectively save the storage and labor cost in the development process, but brings new challenges to the top layer routing at the same time. On this basis, a multi-instantiation top-level routing algorithm based on decision negotiation is designed in this paper, which effectively solves the problems of multi-instantiated block routing, including long routing time and too long path length. In this paper, a non-uniform grid form is proposed to formulate alternative path sets and determine alternative routing channels between endpoints. The decision extraction and decision evaluation algorithms are used to deal with the path redundancy and short circuit problems generated by multiple instantiations. The feasible solution is determined by improved BFS (Breadth First Search) algorithm on the candidate decision set. The optimal solution with the shortest path in Manhattan is determined by iterative decision evaluation in the feasible solution. In order to verify the accuracy and effectiveness of the proposed method, a verification experiment is conducted in this paper for a number of multi-instantiation modules within 100. The experimental results show that the routing time of the proposed multi-instantiation top-level routing algorithm based on decision negotiation is between 0.1s and 3s, and the ratio of the path length to the standard value is over 95%, on the basis of a 100% success ratio. © 2023 IEEE.

关键词： Routing algorithms

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Numerical Study of the VDMOS with an Integrated High-K Gate Dielectric and High-K Dielectric Trench

Numerical Study of the VDMOS with an Integrated High-K Gate ...

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2021 China Semiconductor technology International Conference, CSTIC 2021

作者： Zhang, Zhenyu Yao, Jiafei Guo, Yufeng He, YongChen Liu, JinCheng Gu, Mingyuan Liang, Qicong National and Local Joint Engineering Laboratory of Rf Integration and Micro-assembly Technology Nanjing China

ISBN: (纸本)9781665449458

The VDMOS with an integrated high-k gate dielectric and high - k dielectric trench is investigated in this paper. The high-k (HK) dielectric is applied both for the gate dielectric and trench, which improves the performance without increasing the process complexity. First, HK dielectric trench makes the electric field distribution of the drift region more uniform, thus improving breakdown voltage (BV). Second, the HK dielectric trench assists the depletion of the drift region, thereby increasing the doping concentration of the drift region and decreasing the specific on-resistance (Ron, sp). Third, the HK gate dielectric decreases the threshold voltage (Vth) and increases the transconductance (gm) of the device. Simulation results show that the new VDMOS has a better breakdown, output, and conduction characteristics when compared to the sidewall HK dielectric VDMOS (SWHK VDMOS) and conventional VDMOS (Con VDMOS). © 2021 IEEE.

关键词： High-k dielectric

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A scalable model for on-chip spiral inductors by Space-mapping neural network

A scalable model for on-chip spiral inductors by Space-mappi...

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2023 IEEE International Symposium on Antennas and Propagation, ISAP 2023

作者： Huang, Shiliang Lin, Jie Ying, Shu Gu, Ling Hu, Shanwen Xue, Junjun Wang, Zixuan Cai, Zhikuang Yao, Jiafei Zhang, Jun Guo, Yufeng Anqing Normal University Anqing China Anhui Silimicro Electronics Technology Limited Liability Company Hefei China Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350341140

This paper presents a scalable model for on-chip spiral inductors utilizing the space-mapping neural network (SMNN), built upon an enhanced 1-π equivalent circuit model. To address the inductor drop observed at low frequencies, a series network consisting of two pairs of inductors and resistors is integrated into the 1-π equivalent circuit model. The topology of the SMNN is optimized using the global search capability of the particle swarm optimization (PSO) algorithm, which determines the optimal weights and thresholds for the SMNN. Compared with traditional neural network models, the proposed SMNN reduces the number of neurons required for mapping the input-output nonlinear relationship, leading to enhanced accuracy and reduced modeling time, which takes a mere 10 to 15 seconds. © 2023 IEEE.

关键词： neural network parametric model Particle Swarm Optimization (PSO) scalable models space-mapping spiral inductors

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Stretchable organic electrochemical transistors for sustained high-fidelity electrophysiology and deep learning-assisted sleep monitoring

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Matter 2025年第5期8卷

作者： Pang, Yuncong Li, Yang Gu, Yuzhe Xu, Benfei Zhu, Zihan Wang, Xiaotian Liao, Yuan Huang, Liya Zhao, Qiang State Key Laboratory of Flexible Electronics Nanjing University of Posts & Telecommunications Nanjing210023 China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210003 China

Good-quality sleep is essential for health, yet obstructive sleep apnea (OSA) underscores the limitations of traditional polysomnography, which is costly, complex, and often uncomfortable. Organic electrochemical transistors (OECTs) offer a promising solution for sleep monitoring due to their high transconductance;however, limitations in stretchability, long-term stability, and intelligent data analysis hinder their broader application. Here, a high-performance stretchable OECT that combines a biocompatible ionic liquid-modified conducting polymer channel with an ionogel electrolyte is developed, addressing the trade-off between performance and wearability. This OECT achieves exceptional transconductance (∼2.1 mS), mechanical resilience (30% strain), and long-term stability (>6 months), enabling high-fidelity electrocardiography (ECG) monitoring with a signal-to-noise ratio (SNR) of 35.7 dB. Through the integration of circuit boards and deep learning algorithms, we have established a wearable, stable, and highly accurate wireless system capable of detecting OSA events from single-lead ECG signals, presenting a novel approach for reliable and portable sleep monitoring. © 2025 Elsevier Inc.

关键词： Conducting polymers

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Polarization-encoded neural networks with simplified grating patch

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Science China(Technological Sciences) 2025年第2期68卷 269-277页

作者： Chengyan ZHONG Xiang WANG Lingfei LI Yuanchi CUI Lei XIAO Dawei SONG Junxiong GUO Wen HUANG Yufeng GUO Yu LIU College of Integrated Circuit Science and Engineering Nanjing University of Posts and TelecommunicationsNanjing 210023China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing 210023China College of Integrated Circuits Hangzhou Global Scientific and Technological Innovation Centre Zhejiang UniversityHangzhou 310027China Nanjing Mumusili Technology Co. LTDNanjing 211100China School of Integrated Circuits Tsinghua UniversityBeijing 100084China Institute of Advanced Study School of Electronic Information and Electrical EngineeringChengdu UniversityChengdu 610106China State Key Laboratory of Electronic Thin Films and Integrated Devices School of Integrated Circuit Science and EngineeringUniversity of Electronic Science and Technology of ChinaChengdu 610054China

Optical neural networks(ONNs)offer a promising solution for high-performance,energy-efficient artificial intelligence hardware by leveraging the parallelism and speed of ***,the large-scale implementation of ONNs remains challenging due to the bulky footprint and complex control of optical *** this work,we propose and simulate a plasmonic polarized synaptic architecture that overcomes the diffraction limit and enables ultra-compact *** tuning the polarization state of incident light,the optical transmittance through each plasmonic unit can be dynamically adjusted to represent a synaptic *** plasmonic structures,with features as small as 40 nm,operate well below this limit in the visible spectrum(400-750 nm).Compared with diffraction and interference-based circuit designs,our proposed method achieves a substantial reduction in synaptic density by factors of 150000-fold and 1500-fold,***,we successfully demonstrate a proof-of-concept plasmonic ONN applied to the Canadian Institute for Advanced Research—10 classes(CIFAR-10)dataset using a Visual Geometry Group network with 16 layers(VGG16)*** training for 80 epochs,the network achieves an accuracy of 93%.The polarization-tunable plasmonics paves the way towards scalable ONNs for next-generation artificial intelligence(AI)accelerators and smart sensors.

关键词： optical neural networks polarization dependent nanophotonic ultra-compact devices diffraction limit

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