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检索条件"机构=National and Local Joint Engineering Laboratory of RF integration&Micro-Assembly Technology"

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A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide Input Range of 4.5-35V 8

A 14-ppm/V 1.5-ppm/°C Reference Voltage Source with a Wide ...

引用

8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Du, Yifei Wang, Xin Wu, Wei Han, Zhenhua Qi, Zhiwei Wang, Zixuan Hu, ShanWen Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

This work presents a high-precision and wide-input-range reference voltage source based on a 180nm BCD process. The reference voltage source generates a constant voltage of 2.5V under the supply voltage ranging from 4.5V to 35V. Both a pre-regulator with current extraction, and high-order curvature compensation are proposed in this work. The current extraction circuit greatly improves the stability of output voltage, and the high-order term of VBE in Bipolar Junction Transistor (BJT) is used for temperature compensation to achieve an output voltage with a low temperature coefficient. Simulation results show that a line regulation of 14ppm/V is achieved, and an average temperature coefficient is 1.5ppm/°C over the range of -45°C to 125°C. In addition, the Power Supply Rejection Ratio (PSRR) is 102.82dB at 10Hz. © 2023 IEEE.

关键词： Temperature

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A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution 8

A Wide-Range and High-Linearity Timing Generator with 1.25ps...

引用

8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Chen, Tianyang Wang, Qianyu Wang, Ze Qi, Zhiwei Han, Zhenhua Liu, Lu Hu, Shanwen Nanjing University of Posts and Telecommunications College of Intergrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

In this paper, a wide range and high resolution of the timing generator circuit is introduced. A high precision delay phase locked loop (DLL) technology is proposed, which uses two identical locking loops to offset the static phase error, realizes accurate delay locking and improves the circuit resolution. In the temperature range of -20 80°C, and the test clock signal ranges from 100KHz to 5GHz, the resolution is 1.25ps and covers a timing adjustment range of 10.4ns, with nonlinear INL less than 0.7 LSB and DNL less than 0.5 LSB. © 2023 IEEE.

关键词： Phase locked loops

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A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure 8

A High-Precision Delay Faults Testing Technique Based on the...

引用

8th International Conference on Integrated Circuits and microsystems, ICICM 2023

作者： Liu, Xiaoting Zhang, Xuewei Hong, Haofei Zhou, Guopeng Wang, Zixuan Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350318517

Aiming at the challenge of testing delay faults in through silicon via (TSV) of Chiplets, a high-precision delay faults testing technique based on the improved die wrapper register (DWR) is proposed. Relying on time-to-digital converter (TDC) embedded in the original DWR, transitional signal is propagated in delay chains and conversed into a digital signal to observe whether there is the delay fault. The double delay chains are constructed by two kinds of XOR gates with different delays. The conversion with high precision is achieved by dividing the transition signal into continuous small time-intervals. With the improved test access port controller (TAPC) circuit, the time to configure effective test path is greatly reduced and the delay test can be realized without additional external interfaces. The simulation results demonstrate that delay faults can be detected within the precision of 11.246ps and the time of test configuration is reduced. © 2023 IEEE.

关键词： Frequency converters

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Research on Space-Time Orbital Angular Momentum Antenna Array Based on Sequential Control 13

Research on Space-Time Orbital Angular Momentum Antenna Arra...

引用

13th International Conference on microwave and Millimeter Wave technology, ICMMT 2021

作者： Weijie, Gong Yumei, Chang Zhenliang, Zhou Tao, Zhu Ye, Han National And Local Joint Engineering Laboratory Of RF Integration And Micro-Assembly Technology 9 Wenyuan Rd Nanjing210035 China Nanjing University Of Posts And Telecommunications 9 Wenyuan Rd Nanjing210035 China

ISBN: (纸本)9781665434379

In this paper, the principle and influence factors of orbital angular momentum (OAM) electromagnetic (EM) waves generated by space-time antenna array (STAA) have been studied. A STAA is formed by introducing the time parameter as a new dimension to the traditional antenna array. The amplitude and phase weighting of the traditional antenna array can be easily realized through the time weighting of the STAA, so the OAM can be generated by the STAA. At the same time, in order to show the influence of the radiation characteristics of antenna array on the generation of OAM waves, a circular patch antenna array that can work at 2.45GHz is designed and simulated to verify the proposal. According to the simulation results, one can conclude that, the number of modes of OAM generated by the STAA is determined by the STAA's bandwidth and the frequency of the switching function. More modes of OAM waves can be generated by reducing the switching frequency or broadening the antenna bandwidth. © 2021 IEEE.

关键词： Antenna arrays

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High-Flatness and Broadband Comb Generator Chip 16

High-Flatness and Broadband Comb Generator Chip

引用

16th IEEE International Conference on Solid-State and Integrated Circuit technology, ICSICT 2022

作者： Yang, Wang Qi, Qian Yufeng, Guo Yi, Zhang Nanjing Vocational University of Industry Technology Nanjing China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing China Nanjing University of Posts and Telecommunications Nanjing China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Based on the signal analysis theory, we build a system-level model to explore the correlation between the narrow pulse signal and its frequency property. Using the high frequency InP HBT devices, this paper designed a broadband comb generator chip. Compared with the traditional method, the chip gets the advantages of high flatness, low power consumption and low input power in the form of active monolithic integrated circuit. Simulation results show that this comb generator can cover 0.1GHz~30GHz frequency band, with amplitude flatness under 12.1dBc and power consumption less than 0.5W. © 2022 IEEE.

关键词： Monolithic integrated circuits

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Multi-instantiated Block Top-layer Routing Technique Based on Steiner Tree Algorithm

Multi-instantiated Block Top-layer Routing Technique Based o...

引用

2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Yang, Hang Chen, Junyuan Cai, Zhikuang Guo, Jingjing Guo, Yufeng College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications Nanjing210003 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing210003 China

ISBN: (纸本)9798350304510

As the scale of chips becomes larger and larger, the time and labor cost of the overall design of a large single chip becomes higher and higher. Therefore, it has become a widely adopted solution to divide one large-scale design into several smaller blocks and realize the functions of each block respectively. In this paper, a multi-instantiated block routing technique is proposed based on the improved Steiner tree algorithm. The algorithm divides wire networks into grids and uses FLUTE to construct and decompose the minimum rectangular Steiner tree of all multipin wire networks, which will decompose any multi-pin connection into several two-pin connections. It abstracts the functions of multi-instantiated blocks involved, and adds fixed pins on the edge of them. The routing process will be conducted inside every block respectively. In order to verify the accuracy and validity of the proposed method, a series of verification experiments are carried out, which shows that the proposed multi-instantiated block routing algorithm can effectively reduce the path redundancy caused by multiple pass-throughs in blocks and improve the routing process efficiency. © 2023 IEEE.

关键词： Routing algorithms

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Multi-Instantiation Top-Level Routing Technique Based on Decision Negotiation Algorithm 6

Multi-Instantiation Top-Level Routing Technique Based on Dec...

引用

6th International Conference on Electronics technology, ICET 2023

作者： Yang, Hang Zhang, Xuewei Cai, Zhikuang Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing210003 China Nanjing University of Posts and Telecommunications National and Local Joint Engineering Laboratory of Rf Integration and Micro-Assembly Technology Nanjing210003 China

ISBN: (纸本)9798350337693

With the development of integrated circuit, multi-instantiated block technology is considered as a reliable optimization direction of chip design, which can effectively save the storage and labor cost in the development process, but brings new challenges to the top layer routing at the same time. On this basis, a multi-instantiation top-level routing algorithm based on decision negotiation is designed in this paper, which effectively solves the problems of multi-instantiated block routing, including long routing time and too long path length. In this paper, a non-uniform grid form is proposed to formulate alternative path sets and determine alternative routing channels between endpoints. The decision extraction and decision evaluation algorithms are used to deal with the path redundancy and short circuit problems generated by multiple instantiations. The feasible solution is determined by improved BFS (Breadth First Search) algorithm on the candidate decision set. The optimal solution with the shortest path in Manhattan is determined by iterative decision evaluation in the feasible solution. In order to verify the accuracy and effectiveness of the proposed method, a verification experiment is conducted in this paper for a number of multi-instantiation modules within 100. The experimental results show that the routing time of the proposed multi-instantiation top-level routing algorithm based on decision negotiation is between 0.1s and 3s, and the ratio of the path length to the standard value is over 95%, on the basis of a 100% success ratio. © 2023 IEEE.

关键词： Routing algorithms

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Dual-band and dual-polarized repeater antenna for wearable applications

Dual-band and dual-polarized repeater antenna for wearable a...

引用

2018 IEEE MTT-S International Wireless Symposium, IWS 2018

作者： Li, Kai Xu, Li-Jie Duan, Zhu Tang, Yiming Bo, Yaming National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing University of Posts and Telecommunications Nanjing210023 China Research Center of Applied Electromagnetics Nanjing University of Information Science and Technology Nanjing210044 China

ISBN: (纸本)9781538663462

A novel dual-band repeater antenna is presented for wearable applications in this paper, covering 2.45 GHz (2.4-2.485 GHz) and 5.8 GHz (5.725-5.875 GHz) industrial scientific medical (ISM) bands. By utilizing stacked structure, different polarization properties are achieved at two bands for the proposed antenna. At 2.45 GHz ISM band, circular polarization property is achieved by adopting a truncated patch at the bottom layer, meeting the demands of communication with implants. While at 5.8 GHz ISM band intended for off-body communication, shorted circular patch is introduced, forming a monopole-like radiation pattern with linear polarization property. © 2018 IEEE.

关键词： Directional patterns (antenna)

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Stage Delay Calculation Method Considering Effective Capacitance

Stage Delay Calculation Method Considering Effective Capacit...

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7th International Conference on Electronics technology, ICET 2024

作者： Zha, Peiwen Guo, Jingjing Zhang, Shugang Nanjing University of Posts and Telecommunication National and Local Joint Engineering Laboratory of Rf Intergration and Micro-assembly Technology College of Integrated Circuit Secience and Engineering Nanjing China

ISBN: (纸本)9798350363951

A key part of a static timing tool is its delay calculation engine-responsible for computing delay, slew, and waveform information from models of logic gates and interconnect parasitic. A stage delay calculator includes cell delay and wire delay. In previous studies, they are often independent. With the advancement of technology, the Miller effect and highly resistive load interconnect have increased the interdependency between cell and wire delay calculations. In this paper, we propose a stage delay calculation approach that utilizes effective capacitance(Ceff) to address the computation of delays and waveforms for both cells and wires. Furthermore, machine learning is employed in the calculation of wire delay, modeling the interconnects using Ceffs as a feature. Experimental results demonstrate that the proposed delay calculation method achieves an accuracy within 1.66% of the delays calculated by SPICE. © 2024 IEEE.

关键词： SPICE

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A scalable model for on-chip spiral inductors by Space-mapping neural network

A scalable model for on-chip spiral inductors by Space-mappi...

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2023 IEEE International Symposium on Antennas and Propagation, ISAP 2023

作者： Huang, Shiliang Lin, Jie Ying, Shu Gu, Ling Hu, Shanwen Xue, Junjun Wang, Zixuan Cai, Zhikuang Yao, Jiafei Zhang, Jun Guo, Yufeng Anqing Normal University Anqing China Anhui Silimicro Electronics Technology Limited Liability Company Hefei China Nanjing University of Posts and Telecommunications Nanjing China National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology Nanjing China

ISBN: (纸本)9798350341140

This paper presents a scalable model for on-chip spiral inductors utilizing the space-mapping neural network (SMNN), built upon an enhanced 1-π equivalent circuit model. To address the inductor drop observed at low frequencies, a series network consisting of two pairs of inductors and resistors is integrated into the 1-π equivalent circuit model. The topology of the SMNN is optimized using the global search capability of the particle swarm optimization (PSO) algorithm, which determines the optimal weights and thresholds for the SMNN. Compared with traditional neural network models, the proposed SMNN reduces the number of neurons required for mapping the input-output nonlinear relationship, leading to enhanced accuracy and reduced modeling time, which takes a mere 10 to 15 seconds. © 2023 IEEE.

关键词： neural network parametric model Particle Swarm Optimization (PSO) scalable models space-mapping spiral inductors

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