This paper analyzes the Parallel Packet Switch(PPS) architecture and studies how to guarantee its performance. Firstly a model of Stable PPS (SPPS) is proposed. The constraints of traffic scheduling algorithms, the nu...
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This paper analyzes the Parallel Packet Switch(PPS) architecture and studies how to guarantee its performance. Firstly a model of Stable PPS (SPPS) is proposed. The constraints of traffic scheduling algorithms, the number of switching layers and internal speedup, for both bufferless and buffered SPPS architecture, are theoretically analyzed. Based on these results, an example of designing a scalable SPPS with 1.28T capacity is presented, and practical considerations on implementing the scheduling algorithm are discussed. Simulations are carried out to investigate the validity and delay performance of the SPPS architecture.
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