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22nd International Conference on Innovation in Clouds, Internet and Networks and Workshops, ICIN 2019

作者： Leira, Rafael Gifre, Lluis Gonzalez, Ivan De Vergara, Jorge E. Lopez Aracil, Javier Universidad Autónoma de Madrid Spain Naudit High Performance Computing and Networking S.L. Spain

ISBN: (纸本)9781538683361

Internet measurement and analysis is increasingly challenging as the Internet evolves, primarily due to changing-trends, speed increments or new protocols and ciphers. As such, ad-hoc monitoring equipment comes in handy, albeit cost-effectiveness impedes deployment at a very large scale. As an alternative, big data-based distributed architectures are being proposed for network monitoring and analysis. However, in light of the high throughput currently offered by 100 Gbit/s links, it turns out that state-of-the-art big data solutions fall short of capacity, unless a huge amount of computers are used. In order to effectively tackle that issue, we have created Wormhole: a streaming engine that circumvents existing limitations by distributing the input messages/packets coherently among different off-the-shelf analysis equipment, thus reducing costs and equipment. Should the incoming data rate be larger than the system throughput, a distributed file system can be used for temporary data storage, for subsequent filtering and in-depth analysis. The proposed solution provides on-line real-time monitoring metrics with the ability to gain further insights when required. The prototyped architecture is able to deal with 100 Gbit/s networks and can be easily scaled up to higher rates by just adding more computing nodes and/or by trimming encrypted packet payloads. © 2019 IEEE.

关键词： Big data

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Network performance Monitoring with Flexible Models of Multi-Point Passive Measurements 14

Network Performance Monitoring with Flexible Models of Multi...

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14th International Conference on Network and Service Management, CNSM 2018 and Workshops, 1st International Workshop on high-Precision Networks Operations and Control, HiPNet 2018 and 1st Workshop on Segment Routing and Service Function Chaining, SR+SFC 2018

作者： Perdices, Daniel Muelas, David Pedro, Luis De Vergara, Jorge E. Lopez De Dept. Electronics and Communication Technologies Escuela Politécnica Superior Universidad Autónoma de Madrid Madrid Spain Naudit High Performance Computing and Networking S.L. Madrid Spain

ISBN: (纸本)9783903176140

Many management actions for networking infrastructures require to simultaneously consider the state of several network elements. This is particularly critical in the case of reconfigurable deployments, such as Virtual or Software-Defined Networks, to scale the affected equipment up and prevent performance bottlenecks. In this light, we present dPRISMA (distributed Passive Retrieval of Information, and Statistical Multipoint Analysis), a passive monitoring system intended to fit statistical models for network measurements and raise alarms in the case of extreme behaviors. As distinguishing features, dPRISMA relies on cost-effective multi-point network measurements, and is able to select a suitable parametric model optimizing the trade-off between fitting and complexity. Therefore, it can (i) correlate records collected from several vantage points and detect where performance issues are most likely to appear;(ii) adjust alarms in terms of the probability of events;and (iii) adapt its behavior to dynamic network conditions while presenting a fair identification of anomalous situations. We evaluate dPRISMA with experiments both in virtual environments and with real-world data to provide evidences of its applicability. © 2018 IFIP.

关键词： Virtual reality

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An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks

An FPGA-based approach for packet deduplication in 100 gigab...

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2017 International Conference on Reconfigurable computing and FPGAs, ReConFig 2017

作者： Ruiz, Mario Sutter, Gustavo López-Buedo, Sergio Zazo, Jose Fernando De Vergara, Jorge E. López High Performance Computing and Networking Research Group Escuela Politécnica Superior Universidad Autónoma de Madrid Spain NAUDIT HPCN Spain

ISBN: (纸本)9781538637975

Network traffic monitoring usually faces the problem of packet duplication, which arises when port mirroring is being used. That is, when traffic is copied from the ports of a switch or a router that are being monitored, to a mirror port where a monitoring probe is attached. Thus, a packet can be copied twice, both at the ingress and egress ports, therefore generating duplicates. Information redundancy caused by packet duplication not only leads to increased workloads at the monitoring probes, but also calls for more disk space to store the network traces. Actually, packet duplication may increase 100% the monitoring load. There are different sorts of packet duplication;in this paper we focus on switching duplication, because it is the most common in a network monitoring scenario, where the network probe is attached to a core switch. We present a high performance FPGA architecture that is able to detect and remove duplicated packets in 100 Gbit/s networks. It is based on a 64-bit key and a BRAM-based shift register that allows us to build an element-based sliding window of size up to 79,872 elements. The design targets the Xilinx Virtex UltraScale family, using the integrated 100G Ethernet Subsystem available in such devices, and it has been tested on a VCU108 evaluation kit. © 2017 IEEE.

关键词： Shift registers

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On the impact of TCP segmentation: Experience in VoIP monitoring 15

On the impact of TCP segmentation: Experience in VoIP monito...

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15th IFIP/IEEE International Symposium on Integrated Network and Service Management, IM 2017

作者： Muelas, David De Vergara, Jorge E. López Ramos, Javier García-Dorado, José Luis Aracil, Javier High Performance Computing and Networking Research Group Escuela Politécnica Superior Universidad Autónoma de Madrid Spain Naudit HPCN S.L. Spain

ISBN: (纸本)9783901882890

Quality of Service (QoS) and Experience (QoE) monitoring is a must during the management of services deployed over the Internet. This is particularly critical for Voice over IP (VoIP), as its degradation is immediately perceived by end users. From our experience, we highlight the impact that TCP segmentation exerts on online VoIP monitoring systems. On the one hand, it makes difficult to interpret the segmented signaling messages for application monitoring. On the other hand, complete messages do not provide information about packet level behavior, which is necessary for internetworking layer monitoring. Paradoxically, the Network Management community has not paid much attention to this fact, although it compromises several VoIP management tasks. To fill in this gap, we provide an empirical evaluation of its impact for the most popular VoIP signaling protocols using traces from enterprise networks, and present the architecture and heuristic that we are currently developing to partially solve the effect of the segmentation. Our proposal avoids the overhead of reconstructing the entire data stream and, at the same time, it enables the analysis of the packets that are actually sent. To do so, it maps TCP flags with segmented application messages, and exploits data structures that reduce latency. In this way, our solution paves the way for online monitoring tools that take into account both internetworking and application layers performance. © 2017 IFIP.

关键词： Voice/data communication systems

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A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links

A single-FPGA architecture for detecting heavy hitters in 10...

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2017 International Conference on Reconfigurable computing and FPGAs, ReConFig 2017

作者： Zazo, Jose Fernando Lopez-Buedo, Sergio Ruiz, Mario Sutter, Gustavo NAUDIT HPCN Calle Faraday 7 Madrid28049 Spain High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid28049 Spain

ISBN: (纸本)9781538637975

In network traffic monitoring, a very important analysis is to find heavy hitters. That is, finding those flows that use most resources in a given network link. This information can be very useful for security or traffic management purposes. Though this analysis might seem easy to implement, since it is essentially based on counting, the fact is that doing it at 100 Gbit/s rates is far from trivial. In 100 Gbit/s Ethernet (100 GbE), up to 148 million packets per second can be received, thus making it very difficult to parse packets and maintain counters at such rate. In this paper, we leverage the integrated 100G Ethernet Subsystem available in Xilinx UltraScale devices to implement a heavy hitter detector for 100 GbE in a VCU108 evaluation kit. Thanks to the integration of the Count Sketch algorithm with a priority list and a network packet parser, the proposed architecture is able to work at line rate for average packet sizes bigger than 215 bytes. The work presents a theoretical analysis of the error, as well as the technical details of the proposed solution. The implementation has been validated using real-world traces, obtaining an average error of 1.29%. © 2017 IEEE.

关键词： Ethernet

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On the impact of TCP segmentation: Experience in VoIP monitoring

On the impact of TCP segmentation: Experience in VoIP monito...

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IFIP/IEEE International Symposium on Integrated Network Management

作者： David Muelas Jorge E. López de Vergara Javier Ramos José Luis García-Dorado Javier Aracil High Performance Computing and Networking Research Group Universidad Aut??noma de Madrid Spain High Performance Computing and Networking Research Group Universidad Autonoma de Madrid Madrid Madrid ES Naudit HPCN S.L. Spain

ISBN: (纸本)9781509056583

关键词： Monitoring Tools Algorithm design and analysis Protocols Software algorithms Multimedia communication Software

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Evaluation of the performance challenges in automatic traffic report generation with huge data volumes

arXiv

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arXiv 2018年

作者： Vega, Carlos Miravalls-Sierra, Eduardo Julián-Moreno, Guillermo López de Vergara, Jorge E. Magaña, Eduardo Aracil, Javier NAUDIT High Performance Computing and Networking S.L. Parque Científico de Madrid C/Faraday 7 Madrid28049 Spain Departamento de Tecnología Electrónica y de las Comunicaciones Escuela Politécnica Superior Universidad Autónoma de Madrid C/Francisco Tomás y Valiente 11 Madrid28049 Spain Departamento de Automática y Computación Universidad Pública de Navarra Campus Arrosadia Pamplona Navarra31006 Spain

In this paper we analyze the performance issues involved in the generation of automated traffic reports for large IT infrastructures. Such reports allows the IT manager to proactively detect possible abnormal situations and roll out the corresponding corrective actions. With the ever-increasing bandwidth of current networks, the design of automated traffic report generation systems is very challenging. In a first step, the huge volumes of collected traffic are transformed into enriched flow records obtained from diverse collectors and dissectors. Then, such flow records, along with time series obtained from the raw traffic, are further processed to produce a usable report. As will be shown, the data volume in flow records is very large as well and requires careful selection of the Key performance Indicators (KPIs) to be included in the report. In this regard, we discuss the use of high-level languages versus low-level approaches, in terms of speed and versatility. Furthermore, our design approach is targeted for rapid development in commodity hardware, which is essential to cost-effectively tackle demanding traffic analysis scenarios. RINT Copyright © 2018, The Authors. All rights reserved.

关键词： Network management

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FPGA-based encrypted network traffic identification at 100 Gbit/s

FPGA-based encrypted network traffic identification at 100 G...

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2016 International Conference on Reconfigurable computing and FPGAs, ReConFig 2016

作者： Ruiz, Mario Sutter, Gustavo Lopez-Buedo, Sergio De Vergara, Jorge E. Lopez High-Performance Computing and Networking Research Group Escuela Politécnica Superior Universidad Autónoma de Madrid Spain NAUDIT HPCN Spain

ISBN: (纸本)9781509037070

Network traffic monitoring is becoming increasingly hard to manage due to the ever-growing speed of network links. At 100 Gbit/s, the huge volume of data makes it very difficult to perform online analyses or to store traffic for subsequent forensic investigations. It is therefore mandatory to carry out some kind of filtering and/or capping in the network traffic to be analyzed. Additionally, the fraction of encrypted traffic is relentlessly increasing. For such encrypted traffic, storing the payload is most times useless. In this paper we present an FPGA implementation of a method to identify plain text (that is, human readable) in the network packet payload. The method is based on both detecting bursts of printable ASCII characters and calculating the fraction of these printable characters in the packet payload. This method has proven to be very effective in reducing the amount of information used in traffic analysis, by saving only the headers of packets with encrypted payloads. We leveraged the advantages of high-level languages to reduce development time, though traditional HDL languages were also used to optimize critical areas of the design. The design targets the 100 Gbit/s Ethernet interfaces of Xilinx Virtex UltraScale devices and it is able to detect human-readable packet payloads at line rate, with a high accuracy. © 2016 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications

Automated synthesis of FPGA-based packet filters for 100 Gbp...

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2016 International Conference on Reconfigurable computing and FPGAs, ReConFig 2016

作者： Zazo, Jose Fernando Lopez-Buedo, Sergio Sutter, Gustavo Aracil, Javier NAUDIT HPCN Calle Faraday 7 Madrid28049 Spain High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid28049 Spain

ISBN: (纸本)9781509037070

Monitoring 100 Gbps network links is a challenging task. Packet filtering allows monitoring applications to focus on the relevant data, discarding packets that do not provide any valuable information. However, such a large line rate calls for custom hardware solutions. This work presents a tool for automatically synthesizing packets filters from a custom grammar, which defines filters in a human-readable format. Thanks to parser generators (Bison) and lexical analyzers (Flex), Verilog code is automatically generated from the filter specification. Rules can be applied over a protocol, a protocol field, the packet payload, or a combination of them. The generated filters use standard AXI4-Stream interfaces, which seamlessly integrate in the packet filtering framework that we have developed for the integrated block for 100G Ethernet available in Xilinx Ultrascale devices. We present the results for two proof-of-concept packet filtering designs. Furthermore, filters are fully pipelined, so the full 100 Gb/s rate is guaranteed. As the framework uses a cut-Through approach, latency is kept to a minimum. Finally, the proposed framework allows for the integration of more complex payload-level filters, written in C language with the Vivado-HLS tool. © 2016 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications

Automated synthesis of FPGA-based packet filters for 100 Gbp...

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International Conference on Reconfigurable computing and FPGAs (ReConFig)

作者： Jose Fernando Zazo Sergio Lopez-Buedo Gustavo Sutter Javier Aracil Naudit HPCN Calle Faraday 7 Madrid Spain High-Performance Computing and Networking Research Group Ciudad Universitaria de Cantoblanco Madrid Spain

Monitoring 100 Gbps network links is a challenging task. Packet filtering allows monitoring applications to focus on the relevant data, discarding packets that do not provide any valuable information. However, such a large line rate calls for custom hardware solutions. This work presents a tool for automatically synthesizing packets filters from a custom grammar, which defines filters in a human-readable format. Thanks to parser generators (Bison) and lexical analyzers (Flex), Verilog code is automatically generated from the filter specification. Rules can be applied over a protocol, a protocol field, the packet payload, or a combination of them. The generated filters use standard AXI4-Stream interfaces, which seamlessly integrate in the packet filtering framework that we have developed for the integrated block for 100G Ethernet available in Xilinx Ultrascale devices. We present the results for two proof-of-concept packet filtering designs. Furthermore, filters are fully pipelined, so the full 100 Gb/s rate is guaranteed. As the framework uses a cut-through approach, latency is kept to a minimum. Finally, the proposed framework allows for the integration of more complex payload-level filters, written in C language with the Vivado-HLS tool.

关键词： Protocols Band-pass filters Grammar Monitoring Field programmable gate arrays Metadata Hardware

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