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International Conference on Field Programmable Logic and Applications

作者： M. Ruiz J. Ramos G. Sutter S. López-Buedo J.E. López de Vergara C. Sisterna High-Performance Computing and Networking Research Group Universidad Autónoma de Madrid Spain NAUDIT HPCN Spain Instituto de Investigaciones Antisísmicas Universidad Nacional de San Juan Argentina

Networks are currently essential for computing: It is therefore essential to guarantee the quality of network links in order to ensure a proper operation of computing systems. However, a widespread deployment of network monitoring devices might not be economically feasible. In this paper, we propose the use of Programmable System-on-Chip FPGAs (PSoCs) for enabling a comprehensive testing of networks. Software-only solutions are no longer valid, because the timescales of current networks call for custom-hardware solutions. Thus, we show that PSoCs are a perfect fit for network quality monitoring devices, by mapping the required measurements to the capabilities of such devices. In order to demonstrate the benefits of PSoCs to monitor the quality of network links, we have developed a prototype based on Xilinx Zynq that is capable of measuring the key performance indicators of Gigabit Ethernet networks, namely: available bandwidth, packet loss, delay and jitter. The monitoring probe features GPS-based timestamping, thus enabling the construction of network delay maps. We present the benefits of the proposed approach in terms of cost and simplicity, and we also show how it could be expanded to multi-Gb/s networks.

关键词： Monitoring Clocks Synchronization Delays Field programmable gate arrays Global Positioning System Receivers

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Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes

Leveraging open source platforms and high-level synthesis fo...

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International Conference on ReConFigurable computing and FPGAs, ReConFig 2015

作者： Ruizy, M. Suttery, G. Lopez-Buedo, S. Ramosy, J. De Vergara, J.E. Lopez Aracil, J. NAUDIT HPCN Calle Faraday 7 Madrid28049 Spain High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid28049 Spain

ISBN: (纸本)9781467394062

Nowadays, 10 Gb/s networks are becoming more and more widespread. Consequently, there is an increasing need for testing equipment for those networks, to measure parameters such as throughput, delay, jitter, packet loss rate, etc. Network testing equipment can be either active or passive, depending on whether it injects traffic or simply monitors packets in network links. In this paper we focus on active network probes, particularly those which are based on injection of packet trains. This type of probes have the advantage of causing little interference with existing network traffic, even though they are quite effective to measure several network parameters such as throughput or delay. Here, we take advantage of the open source NetFPGA project to implement a 10 GbE active monitoring probe based on the packet-train technique. In order to reduce development time, we used NetFPGA's OSNT (Open Source Network Tester) monitor project as a starting point, and we also used high-level synthesis tools (namely, Vivado-HLS) to implement the IP core in charge of computing network parameters. Such two design strategies turned out to be very effective both in terms of coding productivity and accuracy of measurements. Actually, the quality of measurements was found to be much better than that obtained with software solutions running on commodity servers, though the development effort was not significantly higher, thanks to the use of open source platforms and high-level synthesis techniques. © 2015 IEEE.

关键词： Ethernet

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Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes

Leveraging open source platforms and high-level synthesis fo...

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International Conference on Reconfigurable computing and FPGAs (ReConFig)

作者： M. Ruiz G. Sutter S. Lopez-Buedo J. Ramos J.E. Lopez de Vergara J. Aracil High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid Spain High-Performance Computing and Networking Research Group Ciudad Universitaria de Cantoblanco Madrid Spain NAUDIT HPCN Madrid Spain

关键词： Monitoring Throughput Delays Generators Probes Hardware Loss measurement

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A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances

A PCIe DMA engine to support the virtualization of 40 Gbps F...

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International Conference on ReConFigurable computing and FPGAs, ReConFig 2015

作者： Zazo, Jose Fernando Lopez-Buedo, Sergio Audzevich, Yury Moore, Andrew W. NAUDIT HPCN Calle Faraday 7 Madrid28049 Spain High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid28049 Spain Computer Laboratory University of Cambridge 15 JJ Thomson Avenue CambridgeCB3 0FD United Kingdom

ISBN: (纸本)9781467394062

Network Function Virtualization (NFV) allows creating specialized network appliances out of general-purpose computing equipment (servers, storage, and switches). In this paper we present a PCIe DMA engine that allows boosting the performance of virtual network appliances by using FPGA accelerators. Two key technologies are demonstrated, SR-IOV and PCI Passthrough. Using these two technologies, a single FPGA board can accelerate several virtual software appliances. The final goal is, in an NFV scenario, to substitute conventional Ethernet NICs by networking FPGA boards (such as NetFPGA SUME). The advantage of this approach is that FPGAs can very efficiently implement many networking tasks, thus boosting the performance of virtual networking appliances. The SR-IOV capable PCIe DMA engine presented in this work, as well as its associated driver, are key elements in achieving this goal of using FPGA networking boards instead of conventional NICs. Both DMA engine and driver are open source, and target the Xilinx 7-Series and UltraScale PCIe Gen3 endpoint. The design has been tested on a NetFPGA SUME board, offering transfer rates reaching 50 Gb/s for bulk transmissions. By taking advantage of SR-IOV and PCI Passthrough technologies, our DMA engine provides transfers rate well above 40 Gb/s for data transmissions from the FPGA to a virtual machine. We have also identified the bottlenecks in the use of virtualized FPGA accelerators caused by reductions in the maximum read request size and maximum payload PCIe parameters. Finally, the DMA engine presented in this paper is a very compact design, using just 2% of a Xilinx Virtex-7 XC7VX690T device. © 2015 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances

A PCIe DMA engine to support the virtualization of 40 Gbps F...

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International Conference on Reconfigurable computing and FPGAs (ReConFig)

作者： Jose Fernando Zazo Sergio Lopez-Buedo Yury Audzevich Andrew W. Moore NAUDIT HPCN Madrid Spain High-Performance Computing and Networking Research Group Ciudad Universitaria de Cantoblanco Madrid Spain Computer Laboratory University of Cambridge Cambridge United Kingdom

关键词： Field programmable gate arrays Home appliances Software Virtual machining Engines Hardware Acceleration

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Using YANG for the dissemination of the Traffic Engineering Database within software defined Elastic Optical Networks

Using YANG for the dissemination of the Traffic Engineering ...

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International Conference on Transparent Optical Networks

作者： J.E. López de Vergara V. López J.P. Fernández-Palacios D. King Ó. González de Dios N. Georgalas A. Farrel D. Michaud Naudit High Performance Computing and Networking Spain Telefónica I+D/GCTO Spain Lancaster University United Kingdom British Telecom UK Old Dog Consulting United Kingdom Escuela Politécnica Superior Universidad Autónoma de Madrid Spain

This paper presents the challenges and purpose of building the Traffic Engineering Database (TED) to facilitate Software Defined control of an Elastic Optical Network (EON). It explains how a standardized protocol and data model can facilitate this and describes a YANG model that has been developed to represent the TED including the representation of nodes, transponders, links, and available media channels available. This model also represents the established connections (Label Switched Paths - LSPs) between endpoints.

关键词： Optical fiber networks Integrated optics Network topology Media Adaptive optics Protocols Data models

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TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces

TNT10G: A high-accuracy 10 GbE traffic player and recorder f...

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2014 International Conference on Reconfigurable computing and FPGAs, ReConFig 2014

作者： Zazo, Jose Fernando Forconesi, Marco Lopez-Buedo, Sergio Sutter, Gustavo Aracil, Javier NAUDIT HPCN Calle Faraday 7 Madrid28049 Spain Computer Laboratory University of Cambridge 15 JJ Thomson Avenue CambridgeCB3 0FD United Kingdom High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid28049 Spain

ISBN: (纸本)9781479959440

In this paper we present TNT10G (multi-Terabyte trace Network Tester), an FPGA-based tool for replaying and capturing massive Ethernet traces at 10 Gb/s. The tool is capable of reproducing and storing terabytes of network traffic at line rate, even if small packets are being used. Moreover, since the design works at low level (XGMII), accuracy is better than 10 ns, and it is also possible to observe and generate anomalous conditions, such as malformed frames, FCS errors, or illegal inter-frame gaps. All such features make TNT10G a truly useful tool for network testing and monitoring at 10 Gb/s. The design uses the NetFPGA-10G platform, although it could be easily ported to other boards since it uses standard AXI buses. The key element to achieve line-rate operation is a custom-developed Linux driver, which works in conjunction with a high-speed DMA backend core from Northwest Logic. Such blocks, together with a RAID0 array of commodity SSD disks, enable operation at 10 Gb/s. Finally, the use of a low-cost academic board together with off-the-shelf components allows for an open, extensible and cost-effective solution, a unique combination not found in commercial products. © 2014 IEEE.

关键词： Field programmable gate arrays (FPGA)

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TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces

TNT10G: A high-accuracy 10 GbE traffic player and recorder f...

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International Conference on Reconfigurable computing and FPGAs (ReConFig)

作者： Jose Fernando Zazo Marco Forconesi Sergio Lopez-Buedo Gustavo Sutter Javier Aracil NAUDIT HPCN Madrid Spain Computer Laboratory University of Cambridge Cambridge United Kingdom High-Performance Computing and Networking Research Group Universidad Autonoma de Madrid Ciudad Universitaria de Cantoblanco Madrid Spain

关键词： Field programmable gate arrays Software Hardware IP networks Clocks Random access memory Accuracy

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performance evaluation of open-source software for traffic traces manipulation and analysis

Infocommunications Journal

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Infocommunications Journal 2012年第3期4卷 1-8页

作者： Retamosa, German Aracil, Javier Naudit High Performance Computing and Networking Faraday 7 28049 Madrid Spain Universidad Autonoma De Madrid 28049 Madrid Francisco Tomas y Valiente 11 Spain

The paper presents a performance evaluation of commonly-used open-source software for manipulation and offlab ENGLline analysis of traffic traces. In traffic analysis, there is a tradelab ENGLoff between either implementing ad-hoc, low-level software that is optimized for performance or using off-the-shelf open-source software written in high-level languages such as Python. Clearly, the former approach has a penalty in development time. While using high-level languages is easier in terms of development, the size of traffic traces is increasing and so is the processing time. We conclude that the use of high-level languages provides similar processing times in comparison with the low-level languages counterpart, provided that a pre-filtering of the traffic can be performed (by means of tcpdump).

关键词： Python

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