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Adaptive critic designs for optimal control of power systems

Adaptive critic designs for optimal control of power systems

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International Conference on Intelligent systems Applications to Power systems (ISAP)

作者： G.K. Venayagamoorthy R.G. Harley Real-Time Power and Intelligent Systems (RTPIS) Laboratory Department of Electrical and Computer Engineering University of Missouri Rolla MO USA School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

The increasing complexity of the modern power grid highlights the need for advanced modeling and control techniques for effective control of excitation, turbine and flexible AC transmission systems (FACTS). The crucial factors affecting the modern power systems today is voltage and load flow control. Simulation studies in the PSCAD/EMTDC environment and realtime laboratory experimental studies carried out are described and the results show the successful control of the power system elements and the entire power system with adaptive and optimal neurocontrol schemes. Performances of the neurocontrollers are compared with the conventional PI controllers for damping under different operating conditions for small and large disturbances

关键词： Programmable control Adaptive control Optimal control Power system control Power systems Power system simulation PSCAD Power system modeling Flexible AC transmission systems Power grids

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Using a Neural Network to Distinguish Between the Contributions to Harmonic Pollution of Non-Linear Loads and the Rest of the Power System

Using a Neural Network to Distinguish Between the Contributi...

引用

Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： J. Mazumdar R. Harley F. Lambert G.K. Venayagamoorthy School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Real-Time Power and Intelligent Systems Laboratory Department of Electrical and Computer Engineering University of Missouri Rolla Rolla MO USA

Harmonics are one of the important power quality measurable quantities. This paper proposes a neural network solution methodology for the problem of measuring the actual amount of harmonic current injected into a power network by a non-linear load. The determination of harmonic currents is complicated by the fact that the supply voltage waveform is distorted by other loads and is rarely a pure sinusoid. Harmonics may therefore be classified as contributions from the load on the one hand and contributions from the power system or supply harmonics on the other hand. A recurrent neural network architecture based method is used to find a way of distinguishing between the load contributed harmonics and supply harmonics, without disconnecting the load from the network. The main advantage of this method is that only waveforms of voltages and currents have to be measured. This method is applicable for both single and three phase loads. This could be fabricated into a commercial instrument that could be installed in substations of large customer loads, or used as a hand-held clip on instrument

关键词： Power system harmonics Neural networks Pollution measurement Distortion measurement Power measurement Current measurement Voltage Instruments Power system measurements Power quality

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An analysis of expressiveness and design issues for the generalized temporal role-based access control model

An analysis of expressiveness and design issues for the gene...

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作者： Joshi, James B. D. Bertina, Elisa Ghafoor, Arif Department of Information Sciences and Telecommunications University of Pittsburgh Pittsburgh PA 15260 United States Department of Computer Science Purdue University West Lafayette IN 47907 United States School of Electrical and Computer Engineering Purdue University West Lafayette IN 47907 United States Department of Information Sciences and Telecommunications School of Information Sciences University of Pittsburgh United States University of Pittsburgh United States Computer Science Department Purdue University United States CERIAS United States San Jose CA United States Microelectronics and Computer Technology Corporation Rutgers University Telcordia Technologies United States School of Electrical and Computer Engineering Purdue University West Lafayette IN United States Distributed Multimedia Systems Laboratory Information Infrastructure Security Research Laboratory United States

The Generalized Temporal Role-Based Access Control (GTRBAC) model provides a comprehensive set of temporal constraint expressions which can facilitate the specification of fine-grained time-based access control policies. However, the issue of the expressiveness and usability of this model has not been previously investigated. In this paper, we present an analysis of the expressiveness of the constructs provided by this model and illustrate that its constraints-set is not minimal. We show that there is a subset of GTRBAC constraints that is sufficient to express all the access constraints that can be expressed using the full set. We also illustrate that a nonminimal GTRBAC constraint set can provide better flexibility and lower complexity of constraint representation. Based on our analysis, a set of design guidelines for the development of GTRBAC-based security administration is presented. © 2005 IEEE.

关键词： Security of data

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Junction temperature measurements in deep-UV light-emitting diodes

Junction temperature measurements in deep-UV light-emitting ...

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2004 MRS Fall Meeting

作者： Xi, Y. Xi, J.-Q. Gessmann, Th. Shah, J.M. Kim, J.K. Schubert, E.F. Fischer, A.J. Crawford, M.H. Bogart, K.H.A. Allerman, A.A. Future Chips Constellation Department of Physics Applied Physics and Astronomy Rensselaer Polytechnic Institute Troy NY 12180 Future Chips Constellation Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy NY 12180 Compound Semiconductor Research Laboratory Sandia National Laboratories Albuquerque NM 87185

The junction temperature of AlGaN/GaN ultraviolet (UV) Light-Emitting Diodes (LEDs) emitting at 295 nm is measured by using the temperature coefficients of the diode forward voltage and emission peak energy. The high-energy slope of the spectrum is explored to measure the carrier temperature. A linear relation between junction temperature and current is found. Analysis of the experimental methods reveals that the diode-forward voltage is the most accurate method (± 3°C). A theoretical model for the dependence of the diode junction voltage (Vj) on junction temperature (T) is developed that takes into account the temperature dependence of the energy gap. A thermal resistance of 87.6 K/W is obtained with the AlGaN/GaN LED sample mounted with thermal paste on a heat sink. © 2005 Materials Research Society.

关键词： Light emitting diodes

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Performance of optimum combining with channel estimation errors

Performance of optimum combining with channel estimation err...

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IEEE Conference on Vehicular Technology (VTC)

作者： B. Kecicioglu M. Torlak A. Kavak Wireless Information Systems Laboratory(WISLAB) Department of Electrical Engineering University of Texas Dallas Richardson TX USA Department of Computer Engineering Kocaeli University Izmir Turkey

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Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

Minimization of secondary effects in SOI: a 32-bit ANT logic...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Wasson Dipti Sanghvi A. Nunez VLSI Systems Design and CAD (VSDCAD) Laboratory Department of Electrical Engineering and Computer Science (EECS) Syracuse University Syracuse NY USA

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

关键词： Minimization Silicon on insulator technology Adders CMOS logic circuits Circuit synthesis CMOS technology Threshold voltage Noise reduction Circuit noise Logic design

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Pre-layout parasitic estimation in interconnects

Pre-layout parasitic estimation in interconnects

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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Advanced enterprise process modelling utilizing ontology semantics

Advanced enterprise process modelling utilizing ontology sem...

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International Conference on Emerging Technologies and Factory Automation (ETFA)

作者： J. Gialelis A.P. Kalogeras C. Alexakos M. Georgoudakis S. Koubias Applied Electronics Laboratory Electrical and Computer Engineering Department University of Patras Rio-Patras Greece Industrial Systems Institute Platani Greece

Ontologies present a state-of-the-art technology for the provision of machine-readable semantics. Its utilization for the annotation of end-to-end enterprise/industrial processes characterizing advanced collaborative business models, largely contributes to enterprise interoperability, flexibility and component reusability. Our work in this paper emphasizes on the use of ontologies in combination with workflows for business process modeling and presents an associated methodology and architecture

关键词： Ontologies Manufacturing industries Collaboration Collaborative work Production Manufacturing processes Enterprise resource planning Service oriented architecture Communication industry Consumer electronics

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Automated average-value modeling of power electronic sources and loads

Automated average-value modeling of power electronic sources...

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3rd International Energy Conversion engineering Conference

作者： Wu, Ning Wasynczuk, Oleg Walters, Eric Lucas, Charles E. Lamm, Peter T. Purdue University West Lafayette IN 47907 United States PC Krause and Associates Inc. West Lafayette IN 47906 United States Air Force Research Laboratory Wright Patterson OH 45433 United States School of Electrical and Computer Engineering 465 Northwestern Ave United States Department of Electrical and Computer Engineering PC Krause and Associates United States Hentschel Center 1220 Potter Drive United States Computer and Networking Services Hentschel Center 1220 Potter Drive United States 1950 Fifth Street Bldg. 18

ISBN: (纸本)1563477343

Power systems that include regelated power-electronic sources and/or loads are susceptible to potentially destabilizing interactions between these components. A variety of techniques and methodologies have been developed to characterize the small- and large-displacement stability of such systems. Perhaps the most common approach is to establish the input/output impedance-versus-frequency characteristics of all sources and loads, whereby Nyquist- and/or Bode-inspired criteria may be used to characterize interconnected system stability. Essential to this methodology is a means of accurately and efficiently determining the input and/or output impedance-versus-frequency characteristics of the power electronic components that comprise the overall system. These frequency-domain characteristics can be established by (I) direct measurement, (2) exercising detailed simulations, or, more commonly, (3) using state-space average-value models. The primary disadvantage of using direct measurements is that the hardware must be available a-priori which makes it difficult and/or expensive to change or tailor the impedance characteristics if instabilities occur. Calculation of the impedance characteristics from detailed simulations is generally time consuming, especially if the low-frequency characteristics are needed, and little insight is gained as to how the impedance characteristics are affected by the various design parameters. Average-value models overcome the previous disadvantages;however, they introduce a new one. In particular, the derivation of an average-value models is typically time consuming, especially if the circuit topology is complex and/or the power converter exhibits multiple load-dependent modes of operation. In this paper, an automated approach of establishing average-value models of power electronic converters of arbitrary complexity is set forth. The user-supplied inputs consist of a standard Spice-like circuit description (branch parameters and network graph

关键词： Power electronics

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Characterizing and comparing prevailing simulation techniques

Characterizing and comparing prevailing simulation technique...

引用

IEEE Symposium on High-Performance computer Architecture

作者： J.J. Yi S.V. Kodakara R. Sendag D.J. Lilja D.M. Hawkins Networking and Computing Systems Group Freescale Semiconductor Inc. Austin TX USA Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA Department of Electrical and Computer Engineering University of Rhode Island Kingston RI USA School of Statistics University of Minnesota Minneapolis MN USA

Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not been evaluated is their accuracy relative to the reference input set, and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize the reduced input set, truncated execution, and sampling simulation techniques while also examining their speed versus accuracy trade-off and configuration dependence. Finally, to illustrate the effect that a technique could have on the apparent speedup results, we quantify the speedups obtained with two processor enhancements. The results show that: 1) the accuracy of the truncated execution techniques was poor for all three characterization methods and for both enhancements, 2) the characteristics of the reduced input sets are not reference-like, and 3) SimPoint and SMARTS, the two sampling techniques, are extremely accurate and have the best speed versus accuracy trade-offs. Finally, this paper presents a decision tree which can help architects choose the most appropriate technique for their simulations.

关键词： Computational modeling computer simulation Sampling methods computer architecture computer networks Statistics Decision trees Testing Performance analysis Microarchitecture

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