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International Symposium on Object-Oriented Real-Time distributed Computing

作者： Michael Stilkerich Jens Schedel Peter Ulbrich Wolfgang Schröder-Preikschat Daniel Lohmann Department of Computer Science 4-Distributed Systems and Operation Systems Friedrich-Alexander-Universitat Erlangen-Nuremberg Germany Department of Computer Science 4- Distributed Systems and Operating Systems Friedrich-Alexander University Erlangen-Nuremberg

Type-safe high-level languages such as Java have not yet found their way into the domain of deeply embedded systems, even though numerous attempts have been made to make these languages cost attractive. One major challenge that remains is the huge existing code base in many industries. Completely reengineering this code base is not viable for cost and time reasons. We present an approach that allows to isolatedly combine legacy software components and safe software components in an embedded system using the two most common communication idioms found in this domain. Our approach allows the developer to freely choose between hardware- and software-based isolation mechanisms. We demonstrate the feasibility of our approach by porting a non-trivial part of a real-world, hard real-time embedded avionics application. Our results show that the cost of this mixed-mode operation is on the same scale as the pure operation.

关键词： Java Runtime Embedded systems Engines Hardware Sensors

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100 Gbit/s End-to-End Communication: Low Overhead On-Demand Protocol Replacement in High Data Rate Communication systems

100 Gbit/s End-to-End Communication: Low Overhead On-Demand ...

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Conference on Local Computer Networks (LCN)

作者： Steffen Büchner Jörg Nolte Alireza Hasani Rolf Kraemer Distributed Systems/Operating Systems Group Cottbus-Senftenberg Cottbus Germany System Design IHP Frankfurt/Oder Germany

To be able to efficiently utilize high data rates of 100 Gbit/s and beyond, protocols must be carefully selected for specific communication parameters. At the same time, communication parameters, such as data rate/latency requirements and the channel quality, are not static. This contradiction can be solved by switching to the best suited protocol when communication parameters change. However, replacing a protocol is a severe interference in an ongoing transmission that can easily cause performance degradation. In this paper, we present a minimal disruptive replacement approach that allows us to replace protocol implementations for an ongoing transmission.

关键词： Protocols Buildings Switches Interference Throughput Runtime

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MyThOS - Scalable OS design for extremely parallel applications

MyThOS - Scalable OS design for extremely parallel applicati...

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IEEE International Conference on Ubiquitous Intelligence and Computing

作者： Randolf Rotta Jorg Nolte Vladimir Nikolov Lutz Schubert Stefan Bonfert Stefan Wesner Distributed Systems and Operating Systems Group Brandenburg University of Technology Inst. of Inform. Resource Management Ulm University

ISBN: (纸本)9781509027729

Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism and minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization, and message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications and elastic compute clouds, is the management of short-living application threads and processes. This paper discusses OS architecture choices based on microkernel, multikernel and distributed systems designs and our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation and activation compared to monolithic systems like Linux while providing a more flexible protection and threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored.

关键词： operating system Architecture High performance computing Many-core

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Failure Identification from Unstable Log Data using Deep Learning

arXiv

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arXiv 2022年

作者： Bogatinovski, Jasmin Nedelkoski, Sasho Wu, Li Cardoso, Jorge Kao, Odej Distributed and Operating Systems Technical University Berlin Germany Huawei Munich Research Munich Germany

The reliability of cloud platforms is of significant relevance because society increasingly relies on complex software systems running on the cloud. To improve it, cloud providers are automating various maintenance tasks, with failure identification frequently being considered. The precondition for automation is the availability of observability tools, with system logs commonly being used. The focus of this paper is log-based failure identification. This problem is challenging because of the instability of the log data and the incompleteness of the explicit logging failure coverage within the code. To address the two challenges, we present CLog as a method for failure identification. The key idea presented herein based is on our observation that by representing the log data as sequences of subprocesses instead of sequences of log events, the effect of the unstable log data is reduced. CLog introduces a novel subprocess extraction method that uses context-aware neural network and clustering methods to extract meaningful subprocesses. The direct modeling of log event contexts allows the identification of failures with respect to the abrupt context changes, addressing the challenge of insufficient logging failure coverage. Our experimental results demonstrate that the learned subprocesses representations reduce the instability in the input, allowing CLog to outperform the baselines on the failure identification subproblems – 1) failure detection by 9-24% on F1 score and 2) failure type identification by 7% on the macro averaged F1 score. Further analysis shows the existent negative correlation between the instability in the input event sequences and the detection performance in a model-agnostic manner. © 2022, CC BY.

关键词： Deep learning

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Accelerating Extra Dimensional Page Walks for Confidential Computing

Accelerating Extra Dimensional Page Walks for Confidential C...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Dong Du Bicheng Yang Yubin Xia Haibo Chen Institute of Parallel and Distributed Systems Shanghai Jiao Tong University Engineering Research Center for Domain-Specific Operating Systems (MoE) Shanghai China Institute of Parallel and Distributed Systems Shanghai Jiao Tong University Shanghai AI Laboratory Engineering Research Center for Domain-Specific Operating Systems (MoE) Shanghai China

To support highly scalable and fine-grained computing paradigms such as microservices and serverless computing better, modern hardware-assisted confidential computing systems, such as Intel TDX and ARM CCA, introduce permission table to achieve fine-grained and scalable memory isolation among different domains. However, it also adds an extra dimension to page walks besides page tables, leading to significantly more memory references (e.g., 4 12 for RISC-V Sv39) 1 . We observe that most costs (about 75%) caused by the extra dimension of page walks are used to validate page table pages. Based on this observation, this paper proposes HPMP (Hybrid Physical Memory Protection), a hardware-software co-design (on RISC-V) that protects page table pages using segment registers and normal pages using permission tables to balance scalability and performance. We have implemented HPMP and Penglai-HPMP (a TEE system based on HPMP) on FPGA with two RISC-V cores (both in-order and out-of-order). Evaluation results show that HPMP can reduce costs by 23.1%–73.1% on BOOM and significantly improve performance on real-world applications, including serverless computing (FunctionBench) and Redis.

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Fast RDMA-based ordered key-value store using remote learned cache 20

Fast RDMA-based ordered key-value store using remote learned...

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Proceedings of the 14th USENIX Conference on operating systems Design and Implementation

作者： Xingda Wei Rong Chen Haibo Chen Engineering Research Center for Domain-specific Operating Systems Ministry of Education China and Institute of Parallel and Distributed Systems Shanghai Jiao Tong University

ISBN: (纸本)9781939133199

RDMA (Remote Direct Memory Access) has gained considerable interests in network-attached in-memory key-value stores. However, traversing the remote tree-based index in ordered stores with RDMA becomes a critical obstacle, causing an order-of-magnitude slowdown and limited scalability due to multiple roundtrips. Using index cache with conventional wisdom--caching partial data and traversing them locally--usually leads to limited effect because of unavoidable capacity misses, massive random accesses, and costly cache *** argue that the machine learning (ML) model is a perfect cache structure for the tree-based index, termed learned cache. Based on it, we design and implement XSTORE, an RDMA-based ordered key-value store with a new hybrid architecture that retains a tree-based index at the server to perform dynamic workloads (e.g., inserts) and leverages a learned cache at the client to perform static workloads (e.g., gets and scans). The key idea is to decouple ML model retraining from index updating by maintaining a layer of indirection from logical to actual positions of key-value pairs. It allows a stale learned cache to continue predicting a correct position for a lookup key. XSTORE ensures correctness using a validation mechanism with a fallback path and further uses speculative execution to minimize the cost of cache misses. Evaluations with YCSB benchmarks and production workloads show that a single XSTORE server can achieve over 80 million read-only requests per second. This number out-performs state-of-the-art RDMA-based ordered key-value stores (namely, DrTM-Tree, Cell, and eRPC+Masstree) by up to 5.9× (from 3.7×). For workloads with inserts, XSTORE still provides up to 3.5× (from 2.7×) throughput speedup, achieving 53M reqs/s. The learned cache can also reduces client-side memory usage and further provides an efficient memory-performance tradeoff, e.g., saving 99% memory at the cost of 20% peak throughput.

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Securing CACC: Strategies for Mitigating Data Injection Attacks

Securing CACC: Strategies for Mitigating Data Injection Atta...

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IEEE Vehicular Networking Conference (VNC)

作者： Michael Wolf Alexander Willecke Johannes-Christian Müller Keno Garlichs Thomas Griebel Lars Wolf Michael Buchholz Klaus Dietmayer Rens W. van der Heijden Frank Kargl Ulm University Institute of Distributed Systems TU Braunschweig Institute-of Operating Systems and Computer Networks Ulm University Institute of Measurement Control and Microtechnology

ISBN: (数字)9781728192215

ISBN: (纸本)9781728192222

Cooperative Adaptive Cruise Control (CACC) is a typical example for cooperative maneuvers of connected, automated vehicles. Safe operation of any such vehicle highly depends on information emitted by the surrounding vehicles as it is processed by the vehicle's longitudinal controller. This opens an attack surface affecting vehicle safety. This paper studies how CACC controllers can be protected against such attacks to ensure the safety of the vehicle and its passengers. This raises the question of how to mitigate injection of false data into the controller by attacks and other forms of vehicle misbehavior. Based on a literature analysis, this paper defines a new categorization for mitigation strategies, discussing their individual strengths, weaknesses and their potential for attack mitigation. This categorization can be used to derive novel ideas for mitigations, for example, an approach with a parameter-dependent reaction of the controller based on a suspiciousness parameter signaled by the Misbehavior Detection System (MDS). Through a simulation study, we show that this approach improves safety and efficiency of the platoon under attack but also identify a fundamental trade-off between these two design goals.

关键词： Sensors Safety Stability analysis Data models Accidents Sensor fusion Actuators

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Internet: A certain insecurity

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Network Security 1995年第9期1995卷 16-19页

作者： Bob Herschberg Edo Roos Lindgreen Delft University of Technology The Netherlands Professor in the chair of Operating Systems and Distributed Systems at Delft University of Technology The Netherlands Ph. D. student at Delft University of Technology The Netherlands

Despite the rapidly increasing popularity of the Internet, many still view this new communication system as a fad that will pass as quickly as it has emerged. In many cases, management defers investments in Internet technology and skills until mañana and a day. Who can blame them? Three decades of experience with the information-technology industry have taught these managers that the economic lifespan of its products and companies is insanely short, and that caution is a successful strategy to avoid irresponsible investments. However, as caution degrades into neglect, management degrades into dismissing new products and services without thoroughly vetting them.

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From Intent to Effect: Tool-Based Generation of Time-Triggered Real-Time systems on Multi-core Processors

From Intent to Effect: Tool-Based Generation of Time-Trigger...

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International Symposium on Object-Oriented Real-Time distributed Computing

作者： Florian Franzmann Tobias Klaus Peter Ulbrich Patrick Deinhardt Benjamin Steffes Fabian Scheler Wolfgang Schröder-Preikschat Chair of Distributed Systems and Operating Systems Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Germany Process Industries and Drives Nuremberg Germany

Although the manual creation of time-triggered schedules for multi-core real-time systems can be a daunting task, state-of-the-art scheduling algorithms are far from being widely used. This suggests that the availability of sound algorithms is only one side of the story: real-time systems have to be groomed substantially before they can serve as input to available algorithms. Moreover, systems engineers struggle with the temporal effects of their design decisions, in addition to the intended timing properties. Therefore, we believe that appropriate tools are the other side of the story. In this paper, we present the multicore extension of the Real-Time systems Compiler, a compiler-based tool that analyses given event-triggered real-time systems and transforms them into time-triggered equivalents. We focus on the challenges and pitfalls in the transition from theory to practical implementation and present concrete solutions to resolve them. Existing algorithms need to be adapted for performance and, at model level, bound together appropriately to be applicable, for example. Our experiments substantiate the effectiveness and scalability of our approach, even for large tasks sets. Finally, lessons learned give an insight into implementation and hardware details and their impact on schedulability.

关键词： Real-time systems Schedules Software Safety Algorithm design and analysis Hardware Job shop scheduling

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Performance analysis of computational approaches to solve Multiple Sequence Alignment

Performance analysis of computational approaches to solve Mu...

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作者： Montañola, Alberto Roig, Concepció Guirado, Fernando Hernández, Porfidio Notredame, Cedric Distributed Computing Group Computer Science and Industrial Engineering Department Universitat de Lleida Lleida Spain Computer Architecture and Operating Systems Department Universitat Autònoma de Barcelona Cerdanyola del Vallès Spain Barcelona Spain

In the biotechnology field, the deployment of the Multiple Sequence Alignment (MSA) problem, which is a high performance computing demanding process, is one of the new challenges to address on the new parallel systems. The aim of this problem is to find similar regions on biological sequences. Furthermore, the goal of MSA applications is to align as much sequences as possible with a level of quality that makes the alignment biologically meaningful. An efficiency study of different MSA implementations, based on T-Coffee (one of the most used MSA aligners), has been performed in order to find new optimizations that may improve the average execution time on multi-core systems. We found that the current parallel implementations have some performance issues, affecting negatively the scalability of the process. Finally, the proposed implementation based on the usage of threads in conjunction with a message-passing library is presented, with the aim to optimize the execution of the MSA problem in multi-core-based clusters. © 2012 Springer Science+Business Media, LLC.

关键词： Message passing

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