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International Conference on Information Networking

作者： Sanghyun Yoo Yo-han Roh In-Chul Song Joo Hyuk Jeon Myoung Ho Kim Hak Soo Kim Jin Hyun Son Young Sang Paik Joo Hyun Han Hyun Ki Jang Department ofElectrical Engineering and Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea Department ofComputer Science and Engineering Hanyang University Ansan South Korea Ubiquitous Computing Laboratory IBM Korea Seoul South Korea

ISBN: (纸本)9788996076117

The advances in ubiquitous computing technologies have given rise to the u-Business, where we obtain business-related context information from ubiquitous devices to adapt to the changes of business environments in a timely manner. In these rapidly changing u-Business environments, we need a mechanism to modify business process schemas, which represent a group of business activities arranged in a meaningful way to give values to the u-Business. We also need a way to migrate running process instances to their new business process schemas. In this paper, we propose a rule-driven approach for dynamic business process schema modification and instance adaptation. The proposed approach uses rules to describe schema modification operations to be applied and rule execution conditions. Business environment changes are encoded in these rules, thus timely schema modification is possible. We also propose a system architecture for realizing this rule-driven approach. We have designed the system architecture by utilizing existing technologies so that the system can be easily implemented.

关键词： Business Ubiquitous computing computer architecture Concrete computer science Pervasive computing Context-aware services Environmental management Runtime Prototypes

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CJ: Enhancing java with safe type conditions 07

CJ: Enhancing java with safe type conditions

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6th International Conference on Aspect-Oriented Software Development

作者： Huang, Shan Shan Zook, David Smaragdakis, Yannis College of Computing Georgia Institute of Technology Department of Computer and Information Science University of Oregon

ISBN: (纸本)1595936157

cJ is an extension of Java that allows supertypes, fields, and methods of a class or interface to be provided only under some static subtyping condition. For instance, a cJ generic class, C, may provide a member method m only when the type provided for parameter P is a subtype of a specific type *** a practical standpoint, cJ adds to generic Java classes and interfaces the ability to express case-specific code. Unlike conditional compilation techniques (e.g., the C/C++ "#ifdef" construct) cJ is statically type safe and maintains the modular type-checking properties of Java generic classes: a cJ generic class can be checked independently of the code that uses it. Just like regular Java, checking a cJ class implies that all uses are safe, under the contract for type parameters specified in the class's *** a specific application, cJ addresses the well-known shortcomings of the Java Collections Framework (JCF). JCF data structures often throw run-time errors when an "optional" method is called upon an object that does not support it. Within the constraints of standard Java, the authors of the JCF had to either sacrifice static type safety or suffer a combinatorial explosion of the number of types involved. cJ avoids both problems, maintaining both static safety and conciseness. Copyright 2007 ACM.

关键词： Java programming language

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A programmable built-in self-test for embedded memory cores

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IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) 2007年第4期24卷 287-311页

作者： Banerjee, Shibaji Chowdhury, Dipanwita Roy Bhattacharya, Bhargab B. Department of Computer Science and Engineering Indian Institute of Technology Kharagpur 721 302 India Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 BT Road Kolkata 700 108 India

A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a programmable BIST architecture is designed. The BIST circuit allows the users to select a vast variety of test algorithms based on their choice. The single BIST circuit is capable of testing different types of memory cores embedded in SOC. The proposed BIST circuit is shared among the different memory cores in an SOC. For this purpose, test wrappers for the shared BIST circuits and the memory cores are designed. Finally, a test scheduling algorithm is developed to reduce the overall test time. Copyright © 2007 by the IETE.

关键词： Built-in self test

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ParalleX: A study of a new parallel computation model

ParalleX: A study of a new parallel computation model

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21st International Parallel and Distributed Processing Symposium, IPDPS 2007

作者： Gao, Guang R. Sterling, Thomas Stevens, Rick Hereld, Mark Zhu, Weirong Department of Electrical and Computer Engineering University of Delaware Center for Advanced Computing Research California Institute of Technology Department of Computer Science Louisiana State University Mathematics and Computer Science Division Argonne National Laboratory

ISBN: (纸本)1424409101

This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing. In this paper, we present the progress of our research on a parallel programming and execution model - mainly, ParalleX. We describe the functional elements of ParalleX, one such model being explored as part of this project. We also report our progress on the development and study of a subset of ParalleX - the LITL-X at University of Delaware. We then present a novel architecture model - Gilgamesh II - as a ParalleX processing architecture. A design point study of Gilgamesh II and the architecture concept strategy are presented. © 2007 IEEE.

关键词： Parallel processing systems

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Determining the effectiveness of the 3D alice programming environment at the computer science i level

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Journal of Educational computing Research 2007年第2期36卷 223-244页

作者： Sykes, Edward R. Sheridan Institute of Technology and Advanced Learning Canada Department of Computer Science School of Applied Computing and Engineering Sciences Sheridan Institute of Technology and Advanced Learning Oakville Ont. L6H 2L1 1430 Trafalgar Road Canada

Student retention in computer science is becoming a serious concern among Educators in many colleges and universities. Most institutions currently face a significant drop in enrollment in computer science. A number of different tools and strategies have emerged to address this problem (e.g., BlueJ, Karel Robot, etc.). Although these tools help to minimize attrition, they have not made significant improvements to this widespread problem. A newcomer to the scene called Alice has been met with positive results by captivating student interest through its rich 3D visual programming environment. During the fall of 2005, Alice, a newly published textbook, and numerous resources were used in computer science I at McMaster University. This article provides an overview of Alice, an assessment of this new course including qualitative surveys, informal observations, and quantitative analysis including student performance score results. Despite numerous technical problems, it was found that the Alice Group exceeded the performance of Comparison Groups: F(1, 93) = 30.322, p < .001 (between C1 and Alice group);F(1, 81) = 4.182, p = .044 (between C2 and Alice Group). © 2007, Baywood Publishing Co., Inc.

关键词： computer Software Student Interests Programming computer science Enrollment Student Attrition Course Descriptions Surveys Student Evaluation Scores Comparative Analysis Course Evaluation Instructional Effectiveness

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computing a planar widest empty α-siphon in o(n3) time

Computing a planar widest empty α-siphon in o(n3) time

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19th Annual Canadian Conference on Computational Geometry, CCCG 2007

作者： Ben-Moshe, Boaz Bhattacharya, Binay K. Das, Sandip Gaur, Daya R. Shi, Qiaosheng Department of Computer Science College of Judea and Samaria 44837 Ariel Israel School of Computing Science Simon Fraser University Burnaby BC V5A 1S6 Canada Advanced Computing and Microelectronics Unit Indian Statistical Institute Calcutta 700 035 India Department of Computer Science University of Lethbridge 4401 University Drive Lethbridge AB T1K 3M4 Canada

Given a set of n points P in the Euclidean plane, we consider the problem of locating a 1-corner polygonal chain X such that minp∈P d(p, X) is maximized. The polygonal chain has the added property that its interior angle is α and it partitions P. In this note we present an algorithm that solves the problem in o(n3) time and space. The previous best running time for this problem was O(n3 log2 n) time [2].

关键词： Chains

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Floorplanning in Modern FPGAs

Floorplanning in Modern FPGAs

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International Conference on VLSI Design

作者： Pritha Banerjee Susmita Sur-Kolay Arijit Bishnu Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Department of Computer Science and Engineering Indian Institute of Technology Kharagpur India

ISBN: (纸本)9780769527628;0769527620

State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithm for ASIC do not suffice. In this paper, we have proposed an algorithm for unified floorplan topology generation and sizing for recent heterogeneous FPGAs. Experimental results on a set of benchmark circuits show that our three step floorplan generation method can produce feasible solutions very fast with 45% improvement in total half perimeter wirelength compared to the very few previous approaches.

关键词： Field programmable gate arrays Application specific integrated circuits Circuit topology Clustering algorithms Simulated annealing Microelectronics computer science computer architecture Algorithm design and analysis Read-write memory

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Measuring variability in sentence ordering for news summarization

Measuring variability in sentence ordering for news summariz...

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11th European Workshop on Natural Language Generation, ENLG 07

作者： Madnani, Nitin Passonneau, Rebecca Ayan, Necip Fazil Conroy, John M. Dorr, Bonnie J. Klavans, Judith L. O'Leary, Dianne P. Schlesinger, Judith D. Department of Computer Science University of Maryland College Park United States Institute for Advanced Computer Studies University of Maryland College Park United States Center for Computational Learning Systems Columbia University United States IDA/Center for Computing Sciences United States College of Information Studies University of Maryland United States

The issue of sentence ordering is an important one for natural language tasks such as multi-document summarization, yet there has not been a quantitative exploration of the range of acceptable sentence orderings for short texts. We present results of a sentence reordering experiment with three experimental conditions. Our findings indicate a very high degree of variability in the orderings that the eighteen subjects produce. In addition, the variability of reorderings is significantly greater when the initial ordering seen by subjects is different from the original summary. We conclude that evaluation of sentence ordering should use multiple reference orderings. Our evaluation presents several metrics that might prove useful in assessing against multiple references. We conclude with a deeper set of questions: (a) what sorts of independent assessments of quality of the different reference orderings could be made and (b) whether a large enough test set would obviate the need for such independent means of quality assessment.

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A master-worker type eigensolver for molecular orbital computations

A master-worker type eigensolver for molecular orbital compu...

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8th International Workshop on Applied Parallel computing, PARA 2006

作者： Sakurai, Tetsuya Kodaki, Yoshihisa Tadano, Hiroto Umeda, Hiroaki Inadomi, Yuichi Watanabe, Toshio Nagashima, Umpei Department of Computer Science University of Tsukuba Tsukuba 305-8573 Japan Graduate School of Systems and Information Engineering University of Tsukuba Tsukuba 305-8573 Japan Core Research for Evolutional Science and Technology Japan Science and Technology Agency Japan Computational Science Research Division National Institute of Advanced Industrial Science and Technology Computing and Communications Center Kyushu University Fukuoka 812-8581 Japan

ISBN: (纸本)9783540757542

We consider a parallel method for solving generalized eigen-value problems that arise from molecular orbital computations. We use a moment-based method that finds several eigenvalues and their corresponding eigenvectors in a given domain, which is suitable for master-worker type parallel programming models. The computation of eigen-values using explicit moments is sometimes numerically unstable. We show that a Rayleigh-Ritz procedure can be used to avoid the use of explicit moments. As a test problem, we use the matrices that arise in the calculation of molecular orbitals. We report the performance of the application of the proposed method with several PC clusters connected through a hybrid MPI and GridRPC system. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Computation theory

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ParalleX: A Study of A New Parallel Computation Model

ParalleX: A Study of A New Parallel Computation Model

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Guang R. Gao Thomas Sterling Rick Stevens Mark Hereld Weirong Zhu Department of Electrical and Computer Engineering University of Delaware USA Center for Advanced Computing Research California Institute of Technology USA Department of Computer Science Louisiana State University USA Mathematics and Computer Science Division Argonne National Laboratory USA

This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing. In this paper, we present the progress of our research on a parallel programming and execution model - mainly, ParalleX. We describe the functional elements of ParalleX, one such model being explored as part of this project. We also report our progress on the development and study of a subset of ParalleX $the LITL-X at University of Delaware. We then present a novel architecture model - Gilgamesh II - as a ParalleX processing architecture. A design point study of Gilgamesh II and the architecture concept strategy are presented.

关键词： Concurrent computing Computational modeling High performance computing Degradation Delay Programming profession Productivity Processor scheduling Memory management Parallel processing

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