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Evaluation of fault attack detection on SRAM-based FPGAs

Evaluation of fault attack detection on SRAM-based FPGAs

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Latin American Test Workshop, LATW

作者： Fabio Benevenuti Fernanda Lima Kastensmidt Graduate Program in Microelectronics (PGMICRO) Universidade Federal do Rio Grande do Sul (UFRGS) Brazil

ISBN: (纸本)9781538604168

In this paper we present an extended fault injection approach to configuration memory of SRAM-based FPGAs consisting of inter frame many bits upsets to be used as an evaluation tool for attack detection capability and countermeasure effectiveness in security sensitive design modules. The work presented in this paper is twofold. First, we present the concept of a fault detection mechanism for SRAM-based FPGAs based on redundancy of functional modules to be placed evenly spaced over the FPGA floorplan and composing a fault detection mesh. On the following, we present the results of fault injection at the configuration memory of a SRAM-based FPGA used to evaluate the detection capability of different configurations of such detection module. To this, fault injection is done flipping many bits in sequence, locally, mimicking a laser attack. To demonstrate this concept, it was implemented in a Xilinx 7 Series device. The detection module used in the experiments was built around a substitution box (S-box) that is part of the Rijndael symmetric cryptography and the Advanced Encryption Standard (AES).

关键词： Field programmable gate arrays Circuit faults Cryptography Fault detection Sensors Redundancy

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Evaluation of a mixed-signal design diversity system under radiation effects

Evaluation of a mixed-signal design diversity system under r...

引用

Latin American Test Workshop, LATW

作者： Carlos J. González Cristiano P. Chenet Matheus Budelon Rafael Galhardo Vaz Odair Gonçalez Tiago R. Balen Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Alegre RS Brazil Institute for Advanced Studies (IEAv) SP Brazil

In this work a data acquisition system, based on a design diversity redundant scheme, is tested under total ionizing dose effects. The data acquisition system is composed by three ADCs and two voters, implementing different levels of diversity (architectural and temporal). This system is implemented on a 130nm commercial mixed-signal programmable SoC (PSoC 5), from Cypress Semiconductor. The system was tested under 60 Co gamma radiation with a dose rate of 1 krad(Si)/h reaching a total dose of 242 krad(Si). One of the system copies presented a significant degradation on its linearity during the irradiation, while the others kept the functionality with less severe degradation, evidencing the advantage of using diversity to improve resilience in mixed-signal redundant systems.

关键词： Degradation Radiation effects Redundancy Circuit faults Hardware Integrated circuits Ionizing radiation

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System energy analysis for shared memory multiprocessing applications

System energy analysis for shared memory multiprocessing app...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Dieison S. Silveira Sergio Bampi Gabriel B. Moro Eduardo H. M. da Cruz Philippe O. A. Navaux Lucas Mello Schnorr Federal University of Rio Grande do Sul - Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul - Brazil Graduate Program in Computing (PPGC)

ISBN: (纸本)9781509061143

This paper presents a detailed energy consumption analysis, considering the energy consumption related to CPU, cache memory and main memory of parallel applications on a 16-core HPC platform. The correlations between energy consumption, speedup, and execution time are also herein presented. Tests are conducted with the NAS parallel benchmarks using three different measurement tools: i) Perf, for the measurement of hardware cache memory events; ii) CACTI, used to estimate the cache memory energy consumption by access; and iii) PCM, for CPU and DRAM energy consumption estimates. Our results show that the lowest overall energy consumption occurs only when all physical cores are used, reducing by 62%, on average, the total system energy consumption when compared to the sequential version for the execution. Moreover, the cache memories results are even better, achieving a reduction of 80% in most of the cases, despite the increase in cache miss rate generated by the increased number of threads.

关键词： Energy consumption Benchmark testing Cache memory Memory management Phase change materials Random access memory Hardware

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A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding

A novel pruned-based algorithm for energy-efficient SATD ope...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Leonardo Bandeira Soares Cláudio Machado Diniz Eduardo Antonio César da Costa Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing (PPGEEC) Catholic University of Pelotas (UCPEL) Pelotas Brazil

This paper proposes a novel approximate computing algorithm for the Sum of Absolute Transformed Differences (SATD) to meet energy efficiency in CMOS accelerator circuits. It is based on the pruning of least significant coefficients in the 2-D Hadamard Transform (HT) which is the most compute intensive kernel in the SATD. The SATD is a metric for block matching that is used in video coding standards like the new High Efficiency Video Coding (HEVC). This metric is used to provide better results in mode decision when compared to the Sum of Absolute Differences (SAD) at the expense of larger amount of arithmetic operations as well as higher energy consumption. We present 6 different approximate SATD 4×4 architectures that were synthesized for a 45 nm PDK. Results for the approximate architecture with 10 discarded HT coefficients show energy per operation reduction of 70.7% and BD-PSNR reduction of just -0.008 dB, for a 1080p video sequence.

关键词： Transforms Approximation algorithms Computer architecture Energy efficiency Video coding Computational efficiency Approximate computing

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Memory energy consumption analyzer for video encoder hardware architectures

Memory energy consumption analyzer for video encoder hardwar...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Livia Amaral Guilherme Povala Marcelo Porto Dieison Silveira Sergio Bampi Federal University of Pelotas Brazil Group of Architectures and Integrated Circuits (GACI) Federal University of Rio Grande do Sul Brazil Graduate Program in Microelectronics (PGMicro)

ISBN: (纸本)9781509061143

The motion estimation stage requires high number of memory accesses, causing high-energy consumption in the video coding process. This results in lower battery lifetime on mobile devices. Thus, solutions to reduce the external memory bandwidth in video coding systems must be used. This work proposes a memory energy consumption analyzer, which estimates the energy consumption related to memory accesses of video encoder systems. This analyzer enables the evaluation of different schemes with data reuse, reference frame compression and memory hierarchy, which are the most used techniques for memory bandwidth reduction and its associated energy consumption. This analyzer is implemented in SystemC, which allows system modeling in a simple and fast way. As a case study of the tool, the developed analyzer was used to evaluate a solution joining a reference frame compressor and a Level C data reuse scheme. The energy consumption results of the evaluated scheme present reduction on both write and read memory operations, reaching a total memory energy consumption reduction of 97.91% when compared to original video encoder without any technique for memory access reduction.

关键词： Energy consumption Memory management Video coding Standards Hardware Random access memory Writing

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Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm

Exploiting approximate adder circuits for power-efficient Ga...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Julio de Oliveira Leonardo Soares Eduardo Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduare Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This paper proposes the exploration of approximate adders for the implementation of power-efficient Gaussian and Gradient filters for Image Processing. The Gaussian filter is a convolution operator which is used to blur images and to remove noise. On the other hand, the Gradient of an image measures how it is changing. Both blocks can be designed in hardware using only shifts and additions. In this work we exploit a set of approximate adders in order to implement energy-efficient filters. The tree of adders of Gaussian and Gradient filters are implemented using one RCA-based approximate adder, as well as an Error-Tolerant Adder ETAI. The approximate architectures are compared to the best precise implementation of the filters. As the Gaussian and Gradient blocks are part of the Canny edge detector algorithm, we have implemented the adder trees of the filters aiming this application. Our main results show that for an efficient power realization of this algorithm, the best strategy consists in the implementation of the Gaussian filter with ETA I adder, and the Gradient filter with the RCA-based adder.

关键词： Adders Filtering algorithms Image edge detection Computer architecture Detectors Kernel

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A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing

A power-efficient imprecise radix-4 multiplier applied to hi...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Guilherme Paim Leonardo Soares Julio F. R. Oliveira Eduardo Costa Sergio Bampi Electronic Engineering - Engineering Center (CEng) Federal University of Pelotas (UFPel) Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (纸本)9781509061143

This paper presents an power-efficient imprecise radix-4 multiplier applied to filtering Hi-Res (High Resolution) audio. The proposed multiplier was based on an imprecise 2×2 (m=2) multiplication block in order to implement optimized 2's complement radix-2 m array multipliers. The imprecise 2×2 multiplication block was previously proposed in literature, and presents as main characteristic a tunable error that enables the building of an imprecise radix-4 multiplier with a reduced number of logic gates. Since in the radix-2 m multiplier architecture the operands are split into groups of m bits, then, the m=2 imprecise multiplier is used as a basic component in its structure. Our work deals with different levels of approximation in the radix-2 m multiplier. We present four different approximate radix-4 multipliers architectures to be used in sequential FIR filters implemented in hardware. The filters are described in VHDL and synthesized for ASIC in Cadence RTL Compiler tool using Nangate 45nm standard cells. The power reports are evaluated using real input vectors from Hi-Res audio sequences in order to obtain valid power dissipation results. The imprecise FIR filters present area and power reductions of up to 5.7% and 12.5% when compared to the precise designs without compromising the Signal to Noise Ratio (SNR) of recorded 24-bit@192kHz Hi-Res audio signals.

关键词： Finite impulse response filters Signal to noise ratio Computer architecture Logic gates MATLAB Periodic structures Power dissipation

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AN EFFICIENT SUB-SAMPLE INTERPOLATOR HARDWARE FOR VP9-10 STANDARDS

AN EFFICIENT SUB-SAMPLE INTERPOLATOR HARDWARE FOR VP9-10 STA...

引用

IEEE International Conference on Image Processing

作者： Guilherme Paim Wagner Penny Jones Goebel Vladimir Afonso Altamiro Susin Marcelo Porto Bruno Zatt Luciano Agostini Federal University of Pelotas (UFPel) - Engineering Center (CEng) - Electronics Engineering Federal University of Pelotas (UFPel) - Group of Architectures and Integrated Circuits (GACI) Federal University of Rio Grande do Sul (UFRGS) - Graduate Program in Microelectronics (PGMicro)

ISBN: (纸本)9781467399623

This paper presents a hardware design for the sub-sample interpolator used in FME (Fractional Motion Estimation) and MC (Motion Compensation) stages according to the VP9 and VP10 video-coding standards. The proposed architecture is able to save hardware resources through an optimized-filter organization whereas reaching high-throughput and low-power dissipation. The hardware design was described in Verilog and synthesized for ASIC technology. The synthesis results were generated for 45nm Nangate standard cells and demonstrate that the developed architecture is able to process 2160p@60fps videos with a power dissipation of 2.34mW focusing on a VP9-10 decoder.

关键词： Hardware Design Fractional Motion Estimation Motion Compensation VP9 VP10 computer hardware design Motion compensation motion estimation Power dissipation Computer hardware Hardware design languages hardware resource

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Within-die and die-to-die variability on 65nm CMOS : Oscillators experimental results 6

Within-die and die-to-die variability on 65nm CMOS : Oscilla...

引用

6th International Workshop on CMOS Variability, VARI 2015

作者： Brito, Juan Pablo Martinez Lubaszewski, Marcelo Bampi, Sergio Graduate Program on Microelectronics PGMICRO - Informatics Institute Federal University of Rio Grande do Sul UFRGS Porto Alegre Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781509000715

This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm2 in each test chip. © 2015 IEEE.

关键词： Dies

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MOSFET stacked-pair test structure for mismatch evaluation by estimating the on-resistance ratio 6

MOSFET stacked-pair test structure for mismatch evaluation b...

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6th International Workshop on CMOS Variability, VARI 2015

作者： Brito, Juan Pablo Martinez Lubaszewski, Marcelo Bampi, Sergio Graduate Program on Microelectronics PGMICRO - Informatics Institute Federal University of Rio Grande do Sul - UFRGS Porto Alegre Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781509000715

This work describes a procedure for evaluating the mismatch between MOSFET transistors in a test array and connected as stacked-pairs. The transistor mismatch is characterized by measuring the gate voltage dependence of the DC voltage established at the middle node of the common-gate MOSFET stacked-pair. This procedure is modeled as the onresistance ratio of these two transistors and it is performed by two simple measurements. Various pieces of information on the MOSFET mismatch characteristics (e.g., channel length variation and threshold voltage variation) can be extracted. The test structure was manufactured in 180nm CMOS technology, and the test array was designed to allow a large number of MOSFET stacked-pairs, from transistors placed in different parts of the layout to vary gradually the distance of the paired FETs. © 2015 IEEE.

关键词： Threshold voltage

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