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A comparative study between FinFET and CMOS-based SRAMs under resistive defects 20

A comparative study between FinFET and CMOS-based SRAMs unde...

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20th IEEE Latin American Test Symposium, LATS 2019

作者： Copetti, T.S. Balen, T.R. Brum, E. Aquistapace, C. Poehls, L. Bolzani Graduate Program on Microelectronics-PGMICRO Universidade Federal Do Rio Grande Do sul Porto Alegre Brazil School of Engineering Pontifical Catholic University of Rio Grande Do sul Porto Alegre Brazil

ISBN: (纸本)9781728117560

Due to several factors, such as Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE), the miniaturization of planar CMOS transistors reached its limit at the 22nm node. To continue the miniaturization process via technology down-scaling, while preserving system reliability and performance, FinFET devices arise as an alternative to substitute the CMOS transistors. Additionally, Static Random-Access Memories (SRAMs) have been increasingly occupying a great part of Systems-on-Chips (SoCs) silicon area. Designed to reach densities at the limit of the manufacturing process, make this component susceptible to manufacturing defects, including resistive defects. Such defects can escape traditional manufacturing tests, because they may cause dynamic faults during circuits' lifetime. In this context, a comparison between a 20nm FinFET-based SRAM block and a commercial 65nm CMOS-based SRAM block focusing on resistive defects is carried out. The behavior of defective cells operating over different temperature sets has been investigated by means of SPICE simulations. Results show an expressively higher occurrence of dynamic faults induced by resistive defects in FinFET-based memories when compared to CMOS technology. © 2019 IEEE.

关键词： Defects

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VLSI Design of Tree-Based Inference for Low-Power Learning Applications

VLSI Design of Tree-Based Inference for Low-Power Learning A...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Brunno A. Abreu Mateus Grellert Sergio Bampi Graduate Program in Microelectronics (PGMICRO) INF-UFRGS Federal University of Rio Grande do Sul Porto Alegre Brazil Department of Informatics and Statistics − INE Federal University of Santa Catarina (UFSC) Florianópolis Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

The use of Machine Learning techniques in battery-powered devices has increased in recent years. Therefore, evaluating power-accuracy trade-offs of inference models has become important. This work explores decision trees architectures, analyzing the effects of model complexity and approximation in power and accuracy. By quantizing the inputs to limited widths, we increased the accuracy of the models in up to 8.7% compared to precise cases. In terms of power, the variation in model complexity was more significant than in input width, as we obtained reductions of up to 97% by decreasing the tree depth, compared to 88% when decreasing the width.

关键词： Complexity theory Hardware Integrated circuit modeling Training Analytical models Decision trees Quantization (signal)

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A 300mV-Supply, 2nW-Power, 80pF-Load CMOS Digital-Based OTA for IoT Interfaces

A 300mV-Supply, 2nW-Power, 80pF-Load CMOS Digital-Based OTA ...

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IEEE International Conference on Electronics, Circuits and Systems

作者： Pedro Toledo Paolo Crovetti Hamilton Klimach Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul Politecnico di Torino

This paper presents a power-efficient Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifier (DB-OTA), which uses static logic gates and processes digitally the analog input signal. Post-layout simulations in 180nm CMOS technology show that at 300mV supply voltage the circuit consumes just 2nW while driving a capacitive load of 80pF with Total Harmonic Distortion lower than 5% at 100mV input signal swing. The total silicon area is 1,426 μm~2. The maximum energy efficiency supply for the DB-OTA and its scalability to 40nm CMOS technology node are also demonstrated.

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Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization

Exploring Architectural Solutions for an Energy-Efficient Ka...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Pedro T. L. Pereira Guilherme Paim Patrícia Ücker Eduardo Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

The Kalman filter is a signal processing algorithm that plays an essential role in real-time mobile applications as nano drones navigation, spacecraft orbit control, GPS positioning, image recognition, and sensor data fusion for wearable health monitoring. However, the Kalman filter is a compute-intensive kernel since it implements a high amount of complex matrix operations like multiplications and inversions. The most timing-consuming tasks of the Kalman filter is the Kalman gain. Therefore, this work presents four architectural solutions to explore real-time and energy-efficient Kalman gain processing.

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Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors

Maximizing the Power-Efficiency of the Approximate Pruned Mo...

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IEEE International New Circuits and Systems Conference

作者： Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

This paper proposes the use of approximate adder compressors for a low-power 8-point Modified Rounded Discrete Cosine Transform (MRDCT_(10)) implementation. The algebraic approximation of the MRDCT was previously introduced in the literature, whose resultant matrix is only composed of 0, 1 and -1 values. Therefore, the MRDCT can be efficiently implemented using only adders and subtractors. We present an environment for the synthesis of the MRDCT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of real images as input vectors to obtain valid power results. Our results show that the use of approximate adder/subtractor compressors in hardwired state-of-the-art 8-point approximate MRDCT_(10) achieves savings ranging from 26% to 52.54% when compared with the macro function (+) from the tool.

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Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Evaluating the Impact of Ionizing Particles on FinFET -based...

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Latin American Test Workshop, LATW

作者： Thiago Copetti Guilherme Cardoso Medeiros Mottaqiallah Taouil Said Hamdioui Letícia Bolzani Poehls Tiago Balen Graduate Program on Microelectronics - PGMICRO Federal University of Rio Grande do Sul Porto Alegre Brazil Computer Engineering Laboratory Delft University of Technology Delft The Netherlands School of Engineering Pontifical Catholic University of Rio Grande do Sul Porto Alegre Brazil

ISBN: (数字)9781728187310

ISBN: (纸本)9781728187327

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET -based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET -based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

关键词： FinFETs SRAM cells Computational modeling Reliability SPICE Transient analysis

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Approximate Sum of Absolute Transformed Differences Hardware Accelerator

Approximate Sum of Absolute Transformed Differences Hardware...

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IEEE International Conference on Electronics, Circuits and Systems

作者： Matheus F. Stigger Victor H. S. Lima Leonardo B. Soares Claudio M. Diniz Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) Rio Grande Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

Motion Estimation and mode decision are the most compute-intensive tasks in recent video encoders. Sum of Absolute Transformed Differences (SATD) is a distortion metric used inside ME and mode decision to decide the best block to be used as prediction for each block to be encoded. To reduce the complexity of SATD calculation, this work proposes an approximate SATD hardware accelerator based on 1D 4 × 4 Hadamard Transform, in contrast with the precise SATD hardware accelerator that contains a 2D 4 × 4 Hadamard Transform. The proposed approximate SATD accelerator reduces power dissipation in 66.86% compared to the precise SATD accelerator while increasing BD-BR only by less than 0.748%, which is a better result than SAD accelerator that increases BD-BR in up to 0.830% compared to precise SATD.

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Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation

Exploiting Partial Distortion Elimination in the Sum of Abso...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Brunno Abreu Gustavo Santana Mateus Grellert Guilherme Paim Leandro Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (纸本)9781538674321

Integer Motion Estimation (IME) is an important tool that explores the temporal redundancies in video encoders. It stands out among the most time-consuming and memory intensive tasks in the encoding process. Most of the IME processing is spent on the computation of similarities between pixel blocks, usually using the Sum of Absolute Differences (SAD) as block selection criterion. Designing high-throughput and energy-efficient SAD units is an effective way of increasing the performance of IME architectures. This paper proposes an optimization of SAD units considering the state-of-the-art High Efficiency Video Coding (HEVC) standard, which avoids the computation of candidates that will surely not be selected in the IME search, by applying Partial Distortion Elimination (PDE). The method achieves, without any loss in coding performance, an average reduction of 16.41% and 11.64% in the energy consumption for 1080p and 2160p (4K) videos, respectively, when compared to an HEVC SAD implementation without PDE.

关键词： Encoding Software Motion estimation Computer architecture Video coding Hardware Software algorithms

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A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation

A Power-Efficient and High-Throughput Hardware Design for 3D...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Murilo Perleberg Vladimir Afonso Ruhan Conceição Altamiro Susin Luciano Agostini Bruno Zatt Marcelo Porto Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This paper presents a hardware design for the 3D-High Efficiency Video Coding (3D-HEVC) Disparity Estimation (DE) based on the Unidirectional Disparity Search (UDS) algorithm. The architecture was developed to process the four square-shaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes. These two design approaches caused a coding efficiency degradation of only 0.554% in the BD-rate when compared to the traditional approach whereas allowed a significant reduction in the required calculations and also in the memory accesses, contributing to generate a fast and energy-efficient design. The architecture has a high level of parallelism to reach the desired high throughput and explored clock gating to reduce the power dissipation. As the best of the author's knowledge, this is the first work on literature presenting a hardware design for the 3D-HEVC DE. The architecture was ASIC synthesized and can reach up to 1.457 GHz. This result allows a processing rate of five views of UHD 2160p videos at 52 frames per second. When compared with related works targeting the HEVC Motion Estimation, the developed architecture uses a smaller area, requires a smaller memory, reaches a higher throughput and dissipates at least 92% less power.

关键词： Encoding Hardware Three-dimensional displays Estimation Tools Video sequences Memory management

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Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4

Low-Power and High-Throughput Architecture for 3D-HEVC Depth...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Mariana Ücker Vladimir Afonso Luan Audibert Altamiro Susin Bruno Zatt Marcelo Porto Luciano Agostini Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (纸本)9781538674321

The 3D-High Efficiency Video Coding (3D-HEVC) is an extension of the High Efficiency Video Coding (HEVC) standard targeting 3D-video encoding. The use of this extension leads to a significant computational-effort increase since new tools are introduced to efficiently encode 3D videos. Therefore, the real-time processing of 3D-videos using 3D-HEVC is highly challenging, and it requires the development of efficient hardware solutions, mainly when mobile devices with energy constraints are considered. This paper focuses on the Depth Modeling Mode 4 (DMM4) encoding mode which is one of the novelties introduced by 3D-HEVC. A low-power and high-throughput architecture was designed and presented in this paper targeting the DMM4, and this architecture was synthesized targeting FPGA and ASIC. The FPGA synthesis was focused on an Altera Stratix V, and the ASIC synthesis was focused on the 45nm Nangate technology. The FPGA and ASIC results showed that the architecture can process UHD 2160p 3D-videos (two views) at 60 fps or to process five views of HD 1080p 3D-videos at 30 frames per second, surpassing the related works in area usage, power dissipation, and processing rate.

关键词： Encoding Tools Calculators Streaming media Computer architecture Field programmable gate arrays Hardware

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