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Performance Modeling of MARE2DEM's Adaptive Mesh Refinement for Makespan Estimation

Performance Modeling of MARE2DEM's Adaptive Mesh Refinement ...

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International Symposium on computer Architecture and High Performance Computing (SBAC-PAD)

作者： Bruno Da Silva Alves Lucas Mello Schnorr Graduate Program in Computer Science (PPGC) Institute of Informatics – UFRGS Porto Alegre Brazil

Adaptive Mesh Refinement (AMR) is a widely known technique to adapt the accuracy of a solution in critical areas of the problem domain instead of using regular or irregular but static meshes. The MARE2DEM is a parallel application that employs the AMR technique to model 2D electromagnetics in oil and gas exploration. The modeling consists in iteratively applying a data inversion based on a set of measurements collected and registered by a survey on an area of interest. The parallelism of the MARE2DEM works by dividing the workload into a set of refinement groups that represent overlapping areas of the problem domain. Each refinement group can be computed independently of the others by a set of workers, carrying out the AMR in the meshes when necessary. The shape and compute performance of the refinement group depend directly of a set of user-defined parameters. In this article, we provide a method to estimate the MARE2DEM performance for all possible values that can be used in the influencing parameters of the application for a given case study. Our relatively cheap method enables the geologist to configure MARE2DEM correctly and extract the best performance for a given cluster configuration. We detail how the method works and evaluate its effectiveness with success, pinpointing the best values for the creating refinement groups using a real case study from the Marlim field on the coast of Rio de Janeiro, Brazil. Although we demonstrate our evaluation with this scenario, our method works for any input of MARE2DEM.

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Fast Intra Mode Decision Using Machine Learning for the Versatile Video Coding Standard

Fast Intra Mode Decision Using Machine Learning for the Vers...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Adson Duarte Bruno Zatt Guilherme Correa Daniel Palomino Video Technology Research Group (ViTech) Graduate Program in Computer Science (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

This paper presents a fast intra mode decision solution for the VVC standard using machine learning. The idea is to reorder the evaluation of modes performed by the Rate-Distortion Optimization (RDO) process according to the modes occurrence rate. Based on the new evaluation order, three Decision Tree models were trained to skip the modes less likely to be chosen. The results show that the proposed solution achieves time savings of up to 15.57% with coding efficiency degradation of only 0.41% on average. When compared with related works, the proposed solution shows competitive results.

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Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture

Optimizing the Montgomery Modular Multiplier for a Power- an...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Mateus Terribele Leme Guilherme Paim Leandro M. G Rocha Patricia Ücker Vitor G. Lima Rafael Soares Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Graduate Program on Computer Science (PPGC) Federal University of Pelotas (UFPel)

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.

关键词： Hardware computer architecture Adders Power dissipation Public key Very large scale integration

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Spatially Adaptive Intra Mode Pre-Selection for ERP 360 Video Coding

Spatially Adaptive Intra Mode Pre-Selection for ERP 360 Vide...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Iago Storch Bruno Zatt Luciano Agostini Guilherme Correa Luis A. da Silva Cruz Daniel Palomino Video Technology Research Group (ViTech) Graduate Program in Computer Science (PPGC) Federal University of Pelotas (UFPel) Brazil Instituto de Telecomunicações University of Coimbra Portugal

ISBN: (数字)9781509066315

ISBN: (纸本)9781509066322

In this work, we propose a spatially adaptive HEVC intra mode pre-selection for equirectangular (ERP) 360 video coding. The proposed technique exploits the spatial characteristics of 360 video in the ERP projection to reduce the complexity of intra prediction mode selection. The number of intra modes evaluated in Rate-Distortion Optimization is reduced based on a score technique that is adaptive to the frame region being encoded. Results show that the proposed technique achieves a complexity reduction of 16.5% with low coding efficiency penalties.

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Online Sharing-Aware Thread Mapping in Software Transactional Memory

Online Sharing-Aware Thread Mapping in Software Transactiona...

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International Symposium on computer Architecture and High Performance Computing (SBAC-PAD)

作者： Douglas Pereira Pasqualin Matthias Diener André Rauber Du Bois Maurício Lima Pilla Computer Science Graduate Program (PPGC) Universidade Federal de Pelotas RS Brazil University of Illinois at Urbana-Champaign IL USA Universidade Federal de Pelotas Pelotas Brazil

ISBN: (数字)9781728199245

ISBN: (纸本)9781728199252

Software Transactional Memory (STM) is an alternative abstraction to synchronize processes in parallel programming. One advantage is simplicity since it is possible to replace the use of explicit locks with atomic blocks. Regarding STM performance, many studies already have been made focusing on reducing the number of aborts. However, in current multicore architectures with complex memory hierarchies, it is also important to consider where the memory of a program is allocated and how it is accessed. This paper proposes the use of a technique called sharing-aware mapping, which maps threads to cores of an application based on their memory access behavior, to achieve better performance in STM systems. We introduce STMap, an online, low overhead mechanism to detect the sharing behavior and perform the mapping directly inside the STM library, by tracking and analyzing how threads perform STM operations. In experiments with the STAMP benchmark suite and synthetic benchmarks, STMap shows performance gains of up to 77% on a Xeon system (17.5% on average) and 85% on an Opteron system (9.1% on average), compared to the Linux scheduler.

关键词： Instruction sets Message systems Multicore processing Software Synchronization Runtime Linux

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Thread Affinity in Software Transactional Memory

Thread Affinity in Software Transactional Memory

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International Symposium on Parallel and Distributed Computing

ISBN: (数字)9781728189468

ISBN: (纸本)9781728189475

Software Transactional Memory (STM) is an abstraction to synchronize accesses to shared resources. It simplifies parallel programming by replacing the use of explicit locks and synchronization mechanisms with atomic blocks. A wellknown approach to improve performance of STM applications is to serialize transactions to avoid conflicts using schedulers and mapping algorithms. However, in current architectures with complex memory hierarchies it is also important to consider where the memory of the program is allocated and how it is accessed. An important technique for improving memory locality is to map threads and data of an application based on their memory access behavior. This technique is called sharing-aware mapping. In this paper, we introduce a method to detect sharing behavior directly inside the STM library by tracking and analyzing how threads perform STM operations. This information is then used to perform an optimized mapping of the application's threads to cores in order to improve the efficiency of STM operations. Experimental results with the STAMP benchmarks show performance gains of up to 9.7x (1.4x on average), and a reduction of the number of aborts of up to 8.5x, compared to the Linux scheduler.

关键词： Instruction sets Synchronization Runtime Symmetric matrices Libraries Benchmark testing

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A NEW HARDWARE FRIENDLY 2D-DCT HEVC COMPLIANT ALGORITHM AND ITS HIGH THROUGHPUT AND LOW POWER HARDWARE DESIGN

A NEW HARDWARE FRIENDLY 2D-DCT HEVC COMPLIANT ALGORITHM AND ...

引用

IEEE International Conference on Electronics, Circuits and Systems

作者： Luciano Almeida Braatz Antonio Carlos Schneider Beck Bruno Zatt Luciano Volcan Agostini Daniel Munari Palomino Marcelo Schiavon Porto Graduate Program in Computer Science (PPGC) Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Brazil Institute of Informatics (INF) Federal University of Rio Grande do Sul (UFRGS) Brazil

This paper presents a hardware-friendly algorithm to maximize the throughput of the Discrete Cosine Transform (DCT) of the High Efficiency Video Coding (HEVC), together with its hardware design. The Fast DCT (FCT) algorithm is based on the Cooley-Tuckey algorithm for the Fast Fourier Transform (FFT) with pre- and post-processing required to maintain the compliance with the HEVC. The resulting algorithm allows high throughput while maintaining low power dissipation. The designed hardware was synthesized for a 45-nm Nangate technology and it reaches a throughput of 81.28GSamples per second when consuming 12.33mW. Such energy efficiency and throughput surpass all related works in the literature.

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Is Intel high performance analytics toolkit a good alternative to Apache Spark?

Is Intel high performance analytics toolkit a good alternati...

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IEEE International Symposium on Network Computing and Applications

作者： Rafael Aquino de Carvalho Alfredo Goldman Gerson Geraldo H. Cavalheiro Institute of Mathematic and Statistic (IME) University of são Paulo (USP) São Paulo Brazil Graduate Program in Computer Science (PPGC) Universidade Federal de Pelotas (UFPel) Pelotas Brazil

This paper compares the performance and stability of two Big Data processing tools: the Apache Spark and the High Performance Analytics Toolkit (HPAT). The comparison was performed using two applications: a unidimensional vector sum and the K-means clustering algorithm. The experiments were performed in distributed and shared memory environments with different numbers and configurations of virtual machines. By analyzing the results we are able to conclude that HPAT has performance improvements in relation to Apache Spark in our case studies. We independently validated the results and potential presented by the HPAT developers. We also provide an analysis of both frameworks in the presence of failures.

关键词： Sparks Big Data Clustering algorithms Databases programming Logistics

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A power-efficient hierarchical network-on-chip topology for stacked 3D ICs

A power-efficient hierarchical network-on-chip topology for ...

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2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013

作者： Matos, Debora Reinbrecht, Cezar Motta, Tiago Susin, Altamiro PPGC -Graduate Program in Computer Science -UFRGS Institute of Informatics Porto Alegre Brazil

ISBN: (纸本)9781479905249

Multi-Processors Systems-on-Chip (MPSoCs) are demanding for high performance, low power and high density, and therefore, three-dimensional integrated circuits (3DIC) emerge as a solution to integrate these systems. In order to appropriately interconnect the layers of these systems in terms of flexibility and scalability, a Network-on-Chip (NoC) is typically employed. In this paper, we argue about the scenario of 3D designs, covering all important issues about this new concept. In agreement with all features discussed in this paper, we have proposed a hierarchical 3D topology that meets well the reality of these designs. Experimental results analyze different topologies and show the large benefits in area and power of our proposal. © 2013 IEEE.

关键词： Network-on-chip

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A power-efficient hierarchical network-on-chip topology for stacked 3D ICs

A power-efficient hierarchical network-on-chip topology for ...

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IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Débora Matos Cezar Reinbrecht Tiago Motta Altamiro Susin PPGC - Graduate Program in Computer Science UFRGS Institute of Informatics Porto Alegre Brazil PPGC - Graduate Program in Computer Science - UFRGS Institute of Informatics Porto Alegre Brazil

关键词： Three-dimensional displays Topology Integrated circuit interconnections Network topology Proposals Through-silicon vias Ports (computers)

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