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High Fluorescence Photosensitive Materials for AOI Inspection of Fan-Out Panel Level package

High Fluorescence Photosensitive Materials for AOI Inspectio...

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Electronic Components and technology Conference (ECTC)

作者： Kiseok Kim Seunghun Chae Jinyoung Kim Jihye Shim Okseon Yoon Sooryeon Kim Material Technology Team Test &amp System Package Samsung Electronics Co. Ltd Cheonan-si Chungcheongnam-do Korea Process Development Team Test &amp

Fan-out panel level package (FOPLP) has been considered as a cost-effective next generation highly integrated IC packaging technology. Therefore, new materials, equipment, and inspection method for fan out package on panel's sizes has been developing. In this study, we have developed new photoimagable dielectric (PID) that improves the AOI overkill by the reflection of the lower layer. AOI consists of visible light and fluorescence test, and fluorescence test detects 450 to 650 nm emitting light after fluorescence reaction by irradiating 405 nm. Conventional material includes a specific additive that reacts with fluorescence at 405 nm, so there is no reflection of lower layer. But it contains the regulated substance, i.e., formaldehyde about 16 ppm (Spec <1 ppm). The new materials have a fluorescence reaction rate of 30% compared to conventional material due to the change of the additive to remove the formaldehyde. But AOI characteristics are equal or higher by using new additive that strongly absorbs UV visible light and light at 480 nm and emits light at 520 nm after fluorescence reaction. In addition, although the absorbance and fluorescence properties are changed, the characteristics such as resolution and physical properties are same as those of conventional material.

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Effect of Dielectric Process on the Interfacial Adhesion of RDL for FOWLP

Effect of Dielectric Process on the Interfacial Adhesion of ...

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Electronic Components and technology Conference (ECTC)

作者： Kirak Son Gahui Kim Young-Bae Park Hyun-Kyu Ryu School of Materials Science and Engineering Andong National University Andong -si Korea Package Technology Development Team SK hynix Inc. Icheon-si Korea

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161815

The effect of low-temperature curable polybenzoxazole (PBO) process conditions on the interfacial adhesion energies between PBO dielectric and Cu redistribution layer for advanced fan-out packaging (FO package) were systematically investigated. The interfacial adhesion energies were 13.8 ± 2.0, 21.7 ± 2.7, and 6.3 ± 0.4 J/m 2 under PBO curing temperature at 175, 200, and 225 °C, respectively. The X-ray photoelectron spectroscopy analysis showed that there exists a good correlation between the interfacial adhesion energy and the O 1s peak area fraction. Also, the nanoindentation analysis showed that there exists a little correlation between the interfacial adhesion energy and the hardness. Therefore, the optimized curing temperature of PBO must be carefully controlled to obtain interfacial adhesion of improvement to achieve interfacial reliability for advanced FO package.

关键词： Adhesives Curing Dielectrics Silicon Temperature Integrated circuits Three-dimensional displays

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Warpage simulation method development considering moiré inhomogeneous temperature field

Warpage simulation method development considering moiré inh...

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International Conference on (ICEPT) Electronic Packaging technology

作者： Zhen Wang Shengxian Li Yonghua Zhou Xiaoqing Li Jun Wu Qiang Chen Package Technology Development Team Samsung Semiconductor (China) R&D CO. LTD Suzhou China

ISBN: (数字)9781728150642

ISBN: (纸本)9781728150659

In this paper, warpage simulation method considering moiré inhomogeneous temperature field is proposed. Shadow moiré is an optical technique for measuring warpage. For moiré inner heating element structure, there is inhomogeneous temperature-field in heating process and the maximum temperature gap at different locations in the same substrate is about 40°C Substrate warpage and inhomogeneous temperatur field impact each other. For previous research about moiré measured results, the influence of inhomogeneous temperature field is not considered. Base of ICEPAK (thermal analysis software) and ABAQUS (structural analysis software), thermal-structural coupled method is studied. According actual temperature field, ICEPAK is used to simulate the moiré cavity thermal radiation temperature field. Moiré temperature field formula is fitted and the fitted formula is used as temperature boundary conditions in ABAQUS to simulate substrate warpage in moiré. Using this method, it is found that warpage simulation result matches well with the moiré measured data and the accuracy of simulation is improved by nearly 50%.

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High Mechanical Dual-Interface FSID COB package development for 15N 3wheel Test

High Mechanical Dual-Interface FSID COB Package Development ...

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第十九届国际电子封装技术会议(ICEPT 2018)

作者： Jianfeng Zeng Haomin Bao Lei Xu Yonghua Zhou Jonghyun Chae Package Development Group Samsung Semiconductor China RD(SSCR)Suzhou China Technology Development Group Samsung Semiconductor China RD(SSCR)Suzhou China Package Technology Dev.Team Samsung Semiconductor China RD(SSCR)Suzhou China

Dual-Interface FSID COB(Chip-On-Board)product has been widely applied in banking *** order to verifying its mechanical performance,there is a 3Wheel test to simulate banking cards use in ATM *** present,the specification of 3Wheel is 100cyc pass with a force of ***,it strongly recommended 100cyc pass with higher force of 15N,in latest CQM(June 2015).Existing Dual-Interface FSID COB has 3Wheel lifetime of less than 50cyc,with a force of *** this paper,simulations were performed to explain mechanism of 15N 3Wheel *** found out largest stress phase and bonding wire stress *** on this,some solutions were developed to reduce wire stress to meet 15N 3Wheel test by changing package structure,material and assembly process.

关键词： COB 3Wheel bonding wire stress

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A preliminary analysis of domain coupling in package power distribution network

A preliminary analysis of domain coupling in package power d...

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IEEE International Workshop on Radio-Frequency Integration technology (RFIT)

作者： Byoungjin Bae Seungwon Kim Youngmin Kim Seokhyeong Kang Il Joon Kim Kwangseok Kim Sunwon Kang Ki Jin Han School of Electrical and Computer Engineering Ulsan National Institute of Science and Technology Ulsan Korea School of Computer and Information Engineering Kwangwoon University Seoul Korea Package Development Team Samsung Electronics Hwaseong Korea

The coupling of power domains in a typical package power distribution network (PDN) is investigated, mainly focusing on the effect of ground structures and substrate parameters. From the simulated impedance parameter data, the self and the coupling capacitances are calculated. The preliminary study shows that the effect of the bottom ground planes has the most dominant effect on the domain coupling, and the ground plane between adjacent power domains can be effectively used to reduce the domain coupling.

关键词： Couplings Ports (Computers) Capacitance Impedance Substrates Structural rings Power systems

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development of Next Generation Flip Chip Interconnection technology Using Homogenized Laser-Assisted Bonding

Development of Next Generation Flip Chip Interconnection Tec...

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Electronic Components and technology Conference (ECTC)

作者： Yanggyoo Jung Dongsu Ryu Minho Gim Choonghoe Kim Yunseok Song Jinyoung Kim Juhoon Yoon Choonheung Lee Package Development Team R&D Center Amkor Technology Korea Inc. Seoul Korea

Conventional flip chip technologies such as the mass reflow (MR) process and the thermal compression bonding (TCB) process are commonly used technologies in the micro assembly field. However, there is a continuous need for next generation interconnection technology to achieve a low form factor with increasing die and substrate complexities. Moreover, very thin 3D integrated packages and 2.5D packages with thin interposer die promise advanced interconnection technologies for mobile and wearable applications. With this point of view, the most important factor in interconnection is optimal thermal energy control for soldering. However, a conventional MR process cannot provide any selectivity and controlled thermal energy transferring with the traditional convection reflow. Its high thermal budget makes warpage an issue, aside from other side effects. To overcome the MR process problems, recent researches and industries have focused on developing a TCB process with non-conductive paste (NCP) or non-conductive film (NCF) due to TCB's unique advantages of low mechanical and thermal stress. However, the productivity of the TCB process is not comparably to the conventional process. Laser-assisted bonding (LAB) with beam homogenizer is considered to be the next generation interconnection technology due to its excellent thermal selectivity, extremely fast ramping up speed with purely controlled wavelength. This LAB process offers a very stable interconnection quality as well as robust functional and reliability result. Interestingly, it also achieves excellent results with thin coreless substrate due to its selective heating area availability. This paper will discuss the laser heating mechanism, multi-chip & component bonding availability and advantage of LAB from an assembly industrial perspective.

关键词： Laser beams Heating Silicon Bonding Absorption Flip-chip devices Substrates

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Mechanism and Process Study for High Performance COB development

Mechanism and Process Study for High Performance COB Develop...

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International Conference on Electronic Packaging technology

作者： Haomin Bao Peng Zhang Yinglei Chen Jiangtao Liu Jianwei Zhou Jonghyun Chae Package Technology Development Team Samsung Semiconductor (China) R&D CO. LTD Suzhou China

ISBN: (纸本)9781509013975

In this paper, the stress distribution and weak point of Au bonding wire in Chip-On-Board (COB) package were analyzed via a stress released model. In order to find out root cause and factors of it, simulations were performed to explain TC failure mechanism and how package styling affected the stress wire suffered. It is found out the stress distribution is related to loop direction. Based on this, new methods were developed to redistribute stress which induced by loop adjustment, neck profile optimization, and encapsulation modification. What is more, the effect of different chip size on stress was also studied. Then, TC performance of each solution were obtained and compared to the normal situation. It demonstrated that TC performance can be obviously enhanced by lowering neck height, increasing neck angle, using small chip and optimizing encapsulation...

关键词： Chip-on-Board Stress Bonding wire Encapsulation TC performance

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Analysis and solution of bump deformation failure in Flip chip process

Analysis and solution of bump deformation failure in Flip ch...

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International Conference on Electronic Packaging technology

作者： Ning Wang Xiaoqing Li Liqun Gu Ying Li Jianwei Zhou Jonghyun Chae Package Technology Development Team Samsung Semiconductor (China) R&D CO. LTD Suzhou China

ISBN: (纸本)9781509013975

In this paper, the root cause and solution of bump deformation failure of memory product in FC (Flip chip) process were studied through experimental and simulation method. After analysis, MUF (Mold under fill) unbalanced flow was proposed to be the real root cause for this type of failure. In order to verificate it, the simulation method was proposed to explain what level of stress did the bump suffer during the mold process. What' more, It was found that all the kinds of products with bump deformation have a larger size of die than those products without bump deformation. So the simulation method was proposed to simulate the MUF flow by different size of die. In order to solve the bump deformation problem, the mold process was optimized. The key parameter which effects the bump deformation was found by DOE. Then the profile was optimized and the result showed that it avoided the bump deformation failure a lot.

关键词： Flip chip Bump deformation EMC flow

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Effects of thermo-compression bonding parameters on joint formation of micro-bumps in non-conductive film (NCF)

Effects of thermo-compression bonding parameters on joint fo...

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Electronic Components and technology Conference (ECTC)

作者： Ji-Won Shin Young Soon Kim Hyoung Gi Lee Un Byung Kang Sun Kyung Seo Kyung-Wook Paik Korea Advanced Institute of Science and Technology (KAIST) Korea Advanced Institute of Science and Technology Daejeon Daejeon KR Package Development team Semiconductor R&D Center Semiconductor Business Samsung Electronics Co. LTD Korea

ISBN: (纸本)9781479986101

Effects of thermo-compression bonding parameter on Cu-pillar/Sn-Ag interconnection reliability of NCF-assembled Chip-on-board (COB) package were investigated. Parallelplate modeling of gap size during the thermo-compression bonding process was performed. By using the viscosity/time graph and the modeling, prediction of gap size was performed in both bare chip to chip and real chip to board. The actually NCF bonding of COB module was performed with different heating rate of 5°C/min, 10°C/min, and 20°C/min. The gap height decreased as the heating rate increased and the results well corresponded with the modeling. All the bonded samples showed stable daisy and contact resistance at as bonded state, however 5°C/min sample showed severe T/C failures due to high gap height and unstable wetting of solder on pad.

关键词： Heating Bonding Viscosity Mathematical model Resins Size measurement Joints

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package embedded decoupling capacitor impact on core power delivery network for ARM SoC application 64

Package embedded decoupling capacitor impact on core power d...

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64th Electronic Components and technology Conference, ECTC 2014

作者： Kim, Gawon Min, Max Sunghwan Yang, Melinda Ling Gundurao, Anil You, Eileen Gill, Harpreet Cha, Seungyong Kim, Younghoon You, Se-Ho Lee, Seungbae Ryu, Woonghwan 85 West Tasman Dr. San JoseCA95134 United States Package Development Team Semiconductor R and D Center Korea Republic of System LSI Division EMI/EMS Lab Korea Republic of System LSI Division Design Technology Team Korea Republic of

ISBN: (纸本)9781479924073

In this paper, a BGA package having a ARM SoC chip is introduced, which has component-type embedded decoupling capacitors (decaps) for good power integrity performance of core power. To evaluate and confirm the impact of embedded decap on core PDN (power distribution network), two different packages were manufactured with and without the embedded decaps. The self impedances of system-level core PDN were simulated in frequency-domain and On-chip DvD (Dynamic Voltage Drop) simulations were performed in timedomain in order to verify the system-level impact of package embedded decap. There was clear improvement of systemlevel core PDN performance in middle frequency range when package embedded decaps were employed. In conclusion, the overall system-level core PDN for ARM SoC could meet the target impedance in frequency-domain as well as the target On-chip DvD level by having package embedded decaps. © 2014 IEEE.

关键词： System-on-chip

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