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Experimental and Numerical Study of Moisture Effect on Warpage of Plastic package

Experimental and Numerical Study of Moisture Effect on Warpa...

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The 15th International Conference on Electronic Packaging technology (ICEPT 2014) ) (第十五届电子封装技术国际会议)

作者： Yinglei Chen Maohua Du Jianwei Zhou Tae Sub Chang Package Technology Development Team Samsung Semiconductor(China)R&D CO. LTD SuzhouChina

In this paper,the moisture effect on the warpage of plastic package is studied through experimental and numerical *** investigations have proved that polymer materials can expand after absorbing *** coefficient of moisture expansion(CME)is proposed to quantitatively describe polymer expansion caused by *** plastic package consists of epoxy molding compound(EMC)and PCB,both of which can easily absorb *** different amounts of moisture absorption in different materials can lead to different expansions,warpage of plastic package can change after moisture absorption,even when the temperature keeps *** the warpage and moisture are monitored during a series of *** the results show similar changing *** CME of EMC and BT core is tested through TGA/TMA *** is found that the CME increases with *** diffusion simulation is used to determine the moisture concentration change of EMC and BT core during the ambient *** results combined with CME are used to calculate the warpage change caused by moisture during the ambient *** simulation results agree with the experiments,verifying the moisture effect on warpage.

关键词： moisture effect warpage change plastic package coefficient of moisture expansion(CME) TGA/TMA method numerical analysis

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A Novel Double Layer NCF for Highly Reliable Micro-Bump Interconnection

A Novel Double Layer NCF for Highly Reliable Micro-Bump Inte...

引用

IEEE Electronic Components and technology Conference

作者： Ji-Won Shin Yong-Won Choi Young Soon Kim Un Byung Kang Sun Kyung Seo Kyung-Wook Paik Dept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology (KAIST) Package Development team Semiconductor R&D Center Semiconductor Business Samsung Electronics Co. LTD

ISBN: (纸本)9781479924080

40 μm pitch Cu-pillar/Sn-Ag bump to Ni pad thermo-compression bonding was performed using non-conductive films (NCFs) with different curing agents. The joint morphology of Cu-pillar/Sn-Ag bump/Ni pad was dependent on the viscosity and curing speed of NCFs. Imidazole NCF with high viscosity and fast curing speed showed no solder wetting on both Cu-pillar and Ni pad. However, anhydride NCF with low viscosity and slow curing speed showed both solder wetting on Cu-pillar and Ni pad. Double layer NCF consisting of imidazole NCF as top layer and anhydride NCF as bottom layer was designed and optimized to eliminate solder wetting on Cu-pillar. Joints bonded using double layer NCF showed ideal joint shape with no solder wetting on Cu pillar and good wetting on pad. Thermal aging at 150℃ was performed and IMC growth rate of Cu6Sn5 and Cu3Sn was slower for double layer NCF compared to single layer NCF due to reduced reacting area for Cu and Sn.

关键词： NCF Novel Double Layer Highly Reliable Micro-Bump Interconnection

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A novel fine pitch TSV interconnection method using NCF with Zn nano-particles

A novel fine pitch TSV interconnection method using NCF with...

引用

Electronic Components and technology Conference (ECTC)

Non-conductive film (NCF) with Zn nano-particles is an effective solution for fine-pitch Cu-pillar/Sn-Ag hybrid bump interconnection in terms of manufacturing process and interfacial reliability. In this study, NCFs with Zn nano-particles of different acidity, viscosity, and curing speed were formulated, and diffused Zn contents in the Cu pillar/Sn-Ag hybrid bumps were measured after 3D TSV chip-stack bonding. Amount of Zn diffusion into the Cu pillar/Sn-Ag bumps increased as the acidity of resin increased, as the viscosity of resin decreased, as the curing speed of resin decreased, and as the bonding temperature increased. Diffusion of Zn nano-particles into the Cu pillar/Sn-Ag bumps are maximized when the resin viscosity became lowered and the solder oxide layer was removed. To analyze the effect of Zn on IMC reduction, NCFs with 0 wt%, 1 wt%, 5 wt%, and 10 wt% of Zn nano-particles were bonded on the test vehicles, and aged at 150°C up to 500 hours. NCF with 10wt% Zn nano-particle showed remarkable suppression in Cu 6 Sn 5 and (Cu, Ni) 6 Sn 5 IMC compared to NCFs with 0 wt%, 1 wt%, and 5 wt% of Zn nano-particles. However, in terms of Cu 3 Sn IMC suppression, which is the most critical goal of this experiment NCFs with 1 wt%, 5wt%, and 10wt% showed an equal amount of IMC suppression. As a result, it was successfully demonstrated that the suppression of Cu-Sn IMCs was achieved by the addition of Zn nano-particles in the NCFs resulting an enhanced reliability performance in the Cu/Sn-Ag hybrid bumps bonding in 3D TSV interconnection.

关键词： Zinc Resins Through-silicon vias Viscosity Curing Bonding Aging

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package embedded decoupling capacitor impact on core power delivery network for ARM SoC application

Package embedded decoupling capacitor impact on core power d...

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Electronic Components and technology Conference (ECTC)

作者： GaWon Kim Max Sunghwan Min Melinda Ling Yang Anil Gundurao Eileen You Harpreet Gill Seungyong Cha Younghoon Kim Se-ho You Seungbae Lee Woonghwan Ryu System LSI SOC Bay Area R&D (SBR) Samsung Semiconductor Inc. San Jose CA USA Package Development Team Semiconductor R&D Center System LSI Division Quality Team EMI/EMS Lab System LSI Division Design Technology Team Samsung Electronics Corporation (SEC)

In this paper, a BGA package having a ARM SoC chip is introduced, which has component-type embedded decoupling capacitors (decaps) for good power integrity performance of core power. To evaluate and confirm the impact of embedded decap on core PDN (power distribution network), two different packages were manufactured with and without the embedded decaps. The self impedances of system-level core PDN were simulated in frequency-domain and On-chip DvD (Dynamic Voltage Drop) simulations were performed in time-domain in order to verify the system-level impact of package embedded decap. There was clear improvement of system-level core PDN performance in middle frequency range when package embedded decaps were employed. In conclusion, the overall system-level core PDN for ARM SoC could meet the target impedance in frequency-domain as well as the target On-chip DvD level by having package embedded decaps.

关键词： System-on-chip Impedance DVD Substrates Frequency-domain analysis Noise Simulation

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development of anhydride-based NCFs for Cu/Sn-Ag eutectic bonding and process optimization for fine pitch TSV chip stacking

Development of anhydride-based NCFs for Cu/Sn-Ag eutectic bo...

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Electronic Components and technology Conference (ECTC)

作者： Ji-Won Shin Yong-Won Choi Young Soon Kim Un Byung Kang Young Kun Jee Ji Hwan Hwang Kyung-Wook Paik Dept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology (KAIST) Package Development team Semiconductor Business Samsung Electronics Co. LTD

Methyl tetrahydrophthalic anhydride (MeTHPA), and Methyl hexahydrophthalic anhydride (MeHHPA) were added as curing agent for bisphenol A/phenoxy resin-based non-conductive film (NCF). Only NCF with MeTHPA showed thermal stability and void-less interface at 250°C, and addition of 0.5 wt% of latent curing accelerator showed minimum NCF cure at pre-bonding stage (120°C) and full NCF cure after main-bonding stage (250°C). The formulated NCF were applied to TSV chip on substrate bonding with Cu/Sn-Ag double bump to Cu pad joint structure. Film thickness and bonding pressure were optimized at 15 μm and 2.4 MPa to form state-of-art joint structure with optimal fillet shape. The joint structures were observed to be stable even after three reliability tests: high temperature storage test (HTST) of 200 hours, pressure cooker test (PCT) of 24 hours, and thermal cycle (T/C) of 200 cycles. Anhydride-based NCF showed stable joints due to flux-ability of anhydride; however, conventional dicyan diamide (DICY) based NCF showed broken joints after T/C due to lack of flux-ability.

关键词： Curing Bonding Joints Through-silicon vias Reliability Resins Films

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Effects of Ag content on electromigration of Sn-Ag solder bumps in C4 package

Effects of Ag content on electromigration of Sn-Ag solder bu...

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IEEE International Workshop Integrated Reliability

作者： Sang-Su Ha Hyunsuk Chun Hyun-Jun Choi Bo-In Noh J. Park Technology Quality and Reliability Quality and Reliability Team Yongin Gyeonggi South Korea Manufacturing Quality and Reliability Quality and Reliability Team Yongin Gyeonggi South Korea Semiconductor Research and Development Center Package Development Team System LSI Business Samsung Electronics Company Limited Yongin Gyeonggi South Korea

ISBN: (纸本)9781467327497

In this study, the effect of Ag content (1.8 & 2.3 wt.%) on the electromigration lifetimes and microstructure evolution of Sn-Ag solder bumps were investigated at highly accelerated electromigration test conditions. Electromigration of solder joint under high current stressing has been an important concern of the reliabilities in solder joint system, since the higher device density and increasing power of flip chip package. The size of the bumps is reduced continuously, causing rapid increase in the current density passing through the bumps. During the high current stressing in solder joints, electromigration failure of the Sn-1.8Ag solder bumps occurred with large consumption of Ni under bump metallization (UBM) and void formation at the cathode side of the solder bump. The electromigration reliability of Sn-2.3Ag solder bumps was superior to that of Sn-1.8Ag solder bumps due to its slow consumption of solder joint and much longer lifetime.

关键词： Cathodes Reliability Nickel Electromigration Resistance Flip chip Current density

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Analysis of die-to-die vertical crosstalk between Clock-tree and Voltage Controlled Oscillator in 3-D IC

Analysis of die-to-die vertical crosstalk between Clock-tree...

引用

IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： Sangrok Lee Kyoungchoul Koo Joungho Kim Terahertz Interconnection and Package Laboratory Department of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) Daejeon South Korea TSV Technology Development Team Hynix Semiconductor Inc. Icheon Kyoungki South Korea

Vertical crosstalk problem between digital and analog circuit components in 3-D IC can severely degrade the 3-D IC system performance. In this paper, we analyze the performance degradation mechanism of 3-D IC that induced by vertical crosstalk between Clock-tree and Voltage Controlled Oscillator (VCO). The 3-D IC test chip which contains Clock-tree and spiral inductor of VCO is fabricated. Lumped component vertical crosstalk model is proposed and it is validated with measurement result. Using validated vertical crosstalk model and spice circuit of VCO, circuit level simulation is performed. Performance degradation mechanism of VCO in 3-D IC is analyzed by separation of noise coupling path approach, and the main mechanism is revealed as high frequency multiplicative noise on signal path.

关键词： Voltage-controlled oscillators Crosstalk Noise Clocks Inductors Spirals Integrated circuits

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Evaluation for UV laser dicing process and its reliability for various designs of stack chip scale package

Evaluation for UV laser dicing process and its reliability f...

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Electronic Components and technology Conference (ECTC)

作者： DoHyung Kim YoonJoo Kim KyeongSool Seong JaeKyu Song BongChan Kim ChanHa Hwang ChoonHeong Lee Application Package Development Team Research and Development center Amkor Technology Korea Inc. Seoul South Korea

In the semiconductor market, the trend of packaging for die stacking technology moves to high density with thinner chips and higher capacity of memory devices. Moreover, the wafer sawing process is becoming more important for thin wafer, because its process speed tends to affect sawn quality and yield. ULK (ultra low-k) device could require laser grooving application to reduce the stress during wafer sawing. Furthermore under 75 mum-thick thin low-k wafer is not easy to use the laser grooving application. So, UV laser dicing technology that is very useful tool for Si wafer was selected as full cut application, which has been being used on low-k wafer as laser grooving method. Therefore, this laser full cut application is emerging to respond wafer sawing method for ultra thin wafer as well as thin ULK wafer. Laser full cut application shows higher process speed than diamond blade saw so that there can be the merit for productivity. And quality problems of conventional blade dicing such as top side chipping, back side chipping and lateral crack can be reduced with this technology. In this study, laser full cut application was evaluated whether this would be applicable to mass production and checked its reliability like T/C (temperature cycle) test with various designs of stack chip scale package by comparing result of the conventional diamond blade sawing method. And evaluations on various laser saw systems and processing methods were implemented to compare die breakage strength because its lower value could cause die broken or crack during the die attach or other processes. Also the productivity such as throughput for ultra thin wafer like less than 75um thickness was analyzed to find the best wafer sawing process which is feasible for mass production.

关键词： Optical design Chip scale packaging Laser beam cutting Laser applications Sawing Blades Semiconductor device packaging Productivity Mass production Semiconductor lasers

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Board level reliability of novel Fan-in package on package(PoP)

Board level reliability of novel Fan-in package on package(P...

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IEEE VLSI Packaging Workshop of Japan, VPWJ

作者： Young-Lyong Kim Cheul-Joong Youn Jong-Ho Lee Hyung-Kil Baek Eun-Chul Ahn Young-Hee Song Tae-Gyeong Chung Packaging Technology Development Team Memory Division Samsung Electronics Company Limited Hwasung South Korea Packaging Technology Development Team Package Development Team Memory Division Samsung Electronics Co. LTD Hwasung-City Gyeonggi-Do Korea

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die package - Dual Stack package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.

关键词： Stacking Electromagnetic compatibility Electronics packaging Life testing Soldering Electronic packaging thermal management Silicon Thermal stresses US Department of Energy Transmission line matrix methods

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Thermo-mechanical reliability of the benzocyclobuten (BCB) film in a WLCSP process

Thermo-mechanical reliability of the benzocyclobuten (BCB) f...

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International Symposium on Electronic Materials and Packaging

作者： K.O. Lee Jin Yu J.Y. Kim I.S. Park Department of Materials Science & Engineering Korea Advanced Institute of Science and Technology Center for Electronic Packaging Materials Daejeon South Korea Advanced package development team Package & Module R & D Center Hynix Semiconductor Inc. South Korea

ISBN: (纸本)0780371577

A new WLCSP process which enables reliable fabrication of high-performance and low cost package has been developed based on the low dielectric passivation layer. The fabrication process can be reduced by using the newly developed photosensitive-BCB and a conventional photolithography process. However, cracks frequently nucleating on the BCB poses serious reliability issues. In order to prevent the crack generation, the stresses in the BCB layer were reduced by optimizing the relative thickness of the BCB and the underlying stress buffer layer(SBL), and by stabilizing the BCB microstructure with optimal photolithography processes. The microstructure of the BCB was investigated by measuring the molecular weight, the cross link element intensity and the glass transition temperature.

关键词： Thermomechanical processes Fabrication Lithography Stress Microstructure Costs Packaging Dielectrics Passivation Weight measurement

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