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Demonstrating self-optimization using a heterogeneous robot group

Demonstrating self-optimization using a heterogeneous robot ...

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IEEE International Conference on Industrial Informatics (INDIN)

作者： Philipp Adelt Bernd Kleinjohann Stefan Herbrechtsmeier Ulrich Rückert C-LAB University of Paderborn Germany System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Germany Cognitronic and Sensor Systems University of Bielefeld Germany

Self-optimization is a concept for mechatronic systems to leave open the choice among system objectives as a degree of freedom until runtime to allow better adaptation to changing system and environment conditions. Demonstration and knowledge transfer of the concept is not easy as the effects of it in mechatronic systems are hard to see in a complex system. To further spread the idea of self-optimization, an intuitive anchor is needed to make it easier to talk about the concept. Also the abstraction from technical details facilitates focusing on the concept. We have developed a multi-agent heterogeneous robotic demonstrator that allows showing the process of self-optimization on a timescale of minutes. The demonstrator decomposes the roles in a mechatronic system to robotic agents. An association between a function and the behavior of the robot is achieved. After having demonstrated the setup for expert and non-expert audiences we have seen the encouraging effect that discussions spin off easily and allow to spread the idea effectively. We present the concept of self-optimization, the behavior-based demonstrator scenario implemented using BeBot miniature and Paderkicker robots in an office environment.

关键词： Mechatronics Control systems Robot sensing systems Sensor systems Actuators Cognitive robotics circuits Runtime environment Knowledge transfer Computer architecture

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Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach

Design of 9T SRAM for dynamic voltage supplies by a multiobj...

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IEEE International Conference on Electronics, circuits and systems (ICECS)

作者： Hans Kristian Otnes Berge Matthias Blesken Snorre Aunet D. Ulrich Rückert Cognitronics and Sensor Systems University of Bielefeld Germany System and Circuit Technology University of Paderborn Germany Department of Informatics University of Oslo Norway

In this paper we present design and optimization results of a 9T SRAM cell in a 65 nm low power technology, which previously has not been investigated for subthreshold operation. The cell is capable of both read and write operations on a supply voltage from 300mV to 1.2V. In our implementation the SRAM cell employs both high and low V t devices for lower leakage and faster read operation. The current work focuses on operation of the cell as a single port SRAM, although extension to dual port is possible. To optimize and find trade-offs for SRAM performance in both voltage domains we use a multiobjective optimization method, where our design goals were robustness, leakage, operating speed and area. The optimization method provides an approximation of the set of all Pareto optimal designs. Based on this we may quickly select criteria for the objectives and easily optimize the rest of the parameters. Compared to recent publications the 9T cell of this paper shows promise of greatly reducing standby leakage power and good robustness while retaining a similar speed.

关键词： Robustness

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High level specification of embedded listeners for monitoring of Network-on-Chips

High level specification of embedded listeners for monitorin...

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IEEE International Symposium on circuits and systems (ISCAS)

作者： Christoph Puttmann Mario Porrmann Paolo R. Grassi Marco D. Santambrogio Ulrich Rückert System and Circuit Technology University of Paderborn Paderborn Germany Computer Science and Engineering Politecnico di Milano Milano Italy Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory Cambridge MA USA Cognitive Interaction Technol. Bielefeld Univ. Bielefeld Germany

Nowadays, the Network-on-Chip (NoC) paradigm has become more and more popular for building an on-chip communication infrastructure. Like in every traditional network, debugging and performance monitoring are also very important issues in NoC-based systems. Unfortunately, the design process of monitoring hardware is a time consuming activity. The work presented in this paper is based on a high level specification language, called SiLLis (Simplified Language for Listeners), for the convenient development of generic monitoring hardware. SiLLis allows the designer to define complex filter rules on a high abstraction level. In this way, the design time as well as the bandwidth requirements for monitoring data can be drastically reduced. To present the benefits of SiLLis, we define a performance monitor that is integrated into a NoC-based multiprocessor system-on-Chip and can be used both to analyze the performance of the system and to optimize the routing strategy at run-time. By using SiLLis, the performance monitor can be realized with a area overhead of only 0.58 % per NoC node.

关键词： Monitoring Network-on-a-chip Hardware Buildings Debugging Process design Specification languages Filters Bandwidth Multiprocessing systems

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Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques

Multiobjective optimization for transistor sizing of CMOS lo...

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2009 NORCHIP

作者： Blesken, Matthias Rückert, Ulrich Steenken, Dominik Witting, Katrin Dellnitz, Michael System and Circuit Technology University of Paderborn Germany Applied Mathematics University of Paderborn Germany

ISBN: (纸本)9781424443109

The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved. ©2009 IEEE.

关键词： Multiobjective optimization

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Using a reconfigurable compute cluster for the acceleration of neural networks

Using a reconfigurable compute cluster for the acceleration ...

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2009 International Conference on Field-Programmable technology, FPT'09

作者： Pohl, Christopher Hagemeyer, Jens Romoth, Johannes Porrmann, Mario Rückert, Ulrich System and Circuit Technology University of Paderborn Fürstenallee 11 33102 Paderborn Germany

ISBN: (纸本)9781424443772

In this paper we present the RAPTOR family as an advanced modular platform for both FPGA-based rapid prototyping and hardware acceleration. Using modern FPGAs and high speed communication links, performance and flexibility of the approach will be shown by means of Kohonens self-organizing map algorithm. This highly parallel algorithm is partitioned onto several FPGAs in different system environments, such as to demonstrate the scalability and the flexibility of the proposed platforms. © 2009 IEEE.

关键词： Field programmable gate arrays (FPGA)

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FPGA-in-the-loop-simulations for dynamically reconfigurable applications

FPGA-in-the-loop-simulations for dynamically reconfigurable ...

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2009 International Conference on Field-Programmable technology, FPT'09

作者： Paiz, C. Pohl, C. Radkowski, R. Hagemeyer, J. Porrmann, M. Rückert, U. System and Circuit Technology University of Paderborn Fürstenallee 11 33102 Paderborn Germany Product Engineering University of Paderborn Fürstenallee 11 33102 Paderborn Germany

ISBN: (纸本)9781424443772

This contribution presents a Hardware-in-the-Loop (HiL) design environment for FPGA-based systems. The presented tool-flow supports a two-stage verification process: A cycle-accurate HiL simulation using well-known simulation tools such as MATLAB/Simulink or Modelsim, and a real-time test using the target environment of the Design Under Test (DUT). The first stage allows an early verification of the DUT using a simulated environment, while the focus of the second stage is on monitoring internal states and I/Os of the DUT in operation, and on adjusting design parameters. All hardware and software interfaces required for both stages are generated individually and automatically by our tool-flow. The demo shows the benefits of using the presented HiL framework for applications targeting dynamic hardware reconfiguration. As an example, a two-controller system for an inverted pendulum is presented, where either a real system or an FPGA-based model combined with an augmented reality 3D animation can be used. © 2009 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Analysis of an ASIC-based coherent polarization-multiplexed QPSK receiver and different receiver frontends 10

Analysis of an ASIC-based coherent polarization-multiplexed ...

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10. ITG-Fachtagung Photonische Netze - 10th ITG Conference on Photonic Networks

作者： El-Darawy, Mohamed Herath, Vijitha Pfau, Timo Hoffmann, Sebastian Peveling, Ralf Adamczyk, Olaf Wördehoff, Christian Rückert, Ulrich Noé, Reinhold Department of Optical Communication and High-Frequency Engineering University of Paderborn EIM-E Paderborn Germany Department of System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Paderborn Germany Nokia Siemens Networks Munich Germany

ISBN: (纸本)9783800731619

In this paper we present the characterization results of an optical coherent quadrature phase shift keying (QPSK) receiver with an application-specific integrated circuit (ASIC) based backend unit. Additionally we investigate the performance of an integrated optical coherent receiver frontend (ICR) and compare it against a fiber-pigtailed 90 optical hybrid. After characterization of the CMOS ASIC, we measure and analyze single polarization QPSK transmission at 2.5 Gbaud with different optical receiver frontend setups. Also we measure the polarization-multiplexed QPSK transmission and discuss the possible reasons for reduced sensitivity compared to the single-polarization transmission. © 2009 10. ITG-Fachtagung.

关键词： Application specific integrated circuits

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Using a reconfigurable compute cluster for the acceleration of neural networks

Using a reconfigurable compute cluster for the acceleration ...

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IEEE International Conference on Field-Programmable technology (FPT)

作者： Christopher Pohl Jens Hagemeyer Johannes Romoth Mario Porrmann Ulrich Rückert System and Circuit Technology University of Paderborn Paderborn Germany

关键词： Computer networks Acceleration Neural networks Hardware Field programmable gate arrays Artificial neural networks Clustering algorithms Emulation Prototypes Partitioning algorithms

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FPGA-in-the-loop-simulations for dynamically reconfigurable applications

FPGA-in-the-loop-simulations for dynamically reconfigurable ...

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IEEE International Conference on Field-Programmable technology (FPT)

作者： C. Paiz C. Pohl R. Radkowski J. Hagemeyer M. Porrmann U. Rückert System and Circuit Technology University of Paderborn Paderborn Germany Product Engineering University of Paderborn Paderborn Germany

This contribution presents a hardware-in-the-loop (HiL) design environment for FPGA-based systems. The presented tool-flow supports a two-stage verification process: A cycle-accurate HiL simulation using well-known simulation tools such as MATLAB/Simulink or Modelsim, and a real-time test using the target environment of the Design Under Test (DUT). The first stage allows an early verification of the DUT using a simulated environment, while the focus of the second stage is on monitoring internal states and I/Os of the DUT in operation, and on adjusting design parameters. All hardware and software interfaces required for both stages are generated individually and automatically by our tool-flow. The demo shows the benefits of using the presented HiL framework for applications targeting dynamic hardware reconfiguration. As an example, a two-controller system for an inverted pendulum is presented, where either a real system or an FPGA-based model combined with an augmented reality 3D animation can be used.

关键词： Mathematical model Testing Clocks Hardware MATLAB Visualization Automatic control Communication system control circuit simulation Augmented reality

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A biologically-inspired and resource-efficient vision system using mobile mini-robots for obstacle avoidance

A biologically-inspired and resource-efficient vision system...

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IEEE International Conference on Robotics and Biomimetics

作者： Teerapat Chinapirom Ulf Witkowski Ulrich Ruckert System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Paderborn Germany

This paper describes a resource-efficient vision system for the mini-robot “Khepera”. It is implemented to perform a fundamental approach of robotic navigation, which is obstacle detection by using an optical flow algorithm. This is inspired by visual perception of insects. The optical flow field is evaluated by implementing the sum of absolute differences (SAD) operation of block matching while the mobile mini-robot moves on texture plane. The SAD is realized in an additional processing module based on a Field Programmable Gate Array (FPGA) solution which can perform various tasks in parallel; for example, image processing, camera control and symbolic protocol transmission to the mini-robot. As a result, the Khepera equipped with 2D camera and the additional module is able to autonomously move avoiding collisions with obstacles, called ego-motion. The 30 × 16 SAD operation is processed by computing 16 pairs of pixels in each operation, which accomplishes the real-time approach. The proposed implementation reduces processing time and power consumption.

关键词： Machine vision Biomedical optical imaging Image motion analysis Field programmable gate arrays Cameras Robots Navigation Visual perception Insects Image processing

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