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14th European Symposium on Artificial Neural Networks, ESANN 2006

作者： Eickhoff, Ralf Sitte, Joaquin Rückert, Ulrich Heinz Nixdorf Institute - System and Circuit Technology University of Paderborn Germany Smart Devices Lab - School of Computing Science and Software Engineering Queensland University of Technology Australia

ISBN: (纸本)2930307064

Artificial neural networks are intended to be used in future nanoelectronics since their biological examples seem to be robust to noise. In this paper, we analyze the robustness of Local Cluster Neural Networks and determine upper bounds on the mean square error for noise contaminated weights and inputs. © 2006 *** publication. All rights reserved.

关键词： Neural networks

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REPLICA2Pro: Task relocation by bitstream manipulation in virtex-II/Pro FPGAs

REPLICA2Pro: Task relocation by bitstream manipulation in vi...

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3rd Conference on Computing Frontiers 2006, CF '06

作者： Kalte, Heiko Porrmann, Mario University of Western Australia School of Computer Science and Software Engineering 35 Stirling Highway Crawley WA 6009 Heinz Nixdorf Institute System and Circuit Technology University of Paderborn 33102 Paderborn Germany

ISBN: (纸本)1595933026

One vision of dynamic hardware reconfiguration is to deliver virtually unlimited hardware resources to a set of hardware tasks implementing arbitrary functions. By using partial reconfiguration, these tasks can be allocated and de-allocated on the reconfigurable architecture while others continue to operate. However, the exact placement of each task can only be determined during runtime according to the current resource allocation. This requires relocating each task from its original position after place and route to an area of available resources. The process of relocating tasks can result in a major time overhead. In order to solve this problem we have developed the REPLICA2Pro (Relocation per online Configuration Alteration in Virtex-2/-Pro) filter, which is capable of performing task relocations by manipulating the task's bitstream during the regular allocation process without any extra time overhead. The filter architecture, our reconfigurable system approach as well as our design flow and an experimental system setup are presented in this paper. Copyright 2006 ACM.

关键词： Field programmable gate arrays (FPGA)

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Bio-Inspired Massively Parallel Architectures for Nanotechnologies

Bio-Inspired Massively Parallel Architectures for Nanotechno...

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Proceedings of 2006 IEEE International Symposium on circuits and systems,Volume 4

作者： Bjorn Jager Mario Porrmann Ulrich Ruckert System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Germany Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Germany

Massively parallel single-chip multiprocessors (CMP) share a number of traits with biological systems such as neural networks. These biological systems have therefore inspired a number of concepts that may help to overcome some of the problems that will come up in future circuit technologies. In this work we present a first comparison of CMPs based on processor cores of different complexity and estimate the efficiency of CMPs with regards to overall performance and energy consumption. The analysis is based on an analytical model of chip multiprocessing that can help to estimate the runtime and energy consumption of different parallel algorithms. As in previous work we will use the GigaNetIC architecture as a basis for the different CMP architectures.

关键词： Parallel architectures Biological systems Energy consumption Nanobioscience Neural networks circuits Algorithm design and analysis Analytical models Runtime Parallel algorithms

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Enhancing Fault Tolerance of Radial Basis Functions

Enhancing Fault Tolerance of Radial Basis Functions

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International Joint Conference on Neural Networks (IJCNN)

作者： R. Eickhoff U. Ruckert Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany

The challenge of future nanoelectronic applications, e.g. in quantum computing or in molecular computing, is to assure reliable computation facing a growing number of malfunctioning and failing computational units. Modeled on biology artificial neural networks are intended to be one preferred architecture for these applications because their architectures allow distributed information processing and, therefore, will result in tolerance to malfunctioning neurons and in robustness to noise. In this work, methods to enhance fault tolerance to permanently failing neurons of Radial Basis Function networks are investigated for function approximation applications. Therefore, a relevance measure is introduced which can be used to enhance the fault tolerance or, on the contrary, to control the network complexity if it is used for pruning.

关键词： Fault tolerance Quantum computing Biology computing Computer architecture Neurons Nanobioscience Molecular computing Biological system modeling Computational biology Artificial neural networks

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Dedicated module access in dynamically reconfigurable systems 06

Dedicated module access in dynamically reconfigurable system...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： J. Hagemeyer B. Kettelhoit M. Porrmann System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Paderborn Germany

ISBN: (纸本)9781424400546

Modern FPGAs, such as the Xilinx Virtex-II series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) during run-time. To enable communication with these modules and for controlling purposes, dedicated access to each module as well as dedicated signals to control the global communication are required. This paper discusses several ways of implementing dedicated signals and addresses the impact on dynamically reconfigurable systems. Two new approaches are introduced, which allow a permanent access to the modules and to the communication infrastructure even during reconfiguration

关键词： Hardware Field programmable gate arrays Runtime Communication system control Reconfigurable logic Shape Clocks circuits Global communication Routing

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SIRENS: A Simple Reconfigurable Neural Hardware Structure for artificial neural network implementations

SIRENS: A Simple Reconfigurable Neural Hardware Structure fo...

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International Joint Conference on Neural Networks (IJCNN)

作者： R. Eickhoff T. Kaulmann U. Ruckert Department of System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Germany

Artificial neural networks are used in various applications and research areas. Mathematically inspired approaches use these types of networks to solve complex classification or function approximation tasks whereas biologically motivated models attempt to adapt desired properties from biology such as robustness or fault tolerance to technical systems and architectures. Therefore, a great variety of different models have been proposed in literature which can be separated in time-dependent and time-independent models. To verify these models and to accelerate simulations prototypes are often implemented in integrated circuits using digital or analog designs. In this work, a simple reconfigurable neural hardware structure (SIRENS) is introduced which is capable to represent several different models of neurons, time-independent and time-dependent models as well. Therefore, this system can be used for several applications (classification or simulation) and purposes (acceleration or operation). The underlying mathematical principles are presented and, furthermore, design considerations are given in this paper.

关键词： Neural network hardware Artificial neural networks Biological system modeling Integrated circuit modeling Acceleration circuit simulation Function approximation Mathematical model systems biology Computational biology

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Adaptable switch boxes as on-chip routing nodes for networks-on-chip

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IFIP Advances in Information and Communication technology 2005年 184卷 201-210页

作者： Eickhoff, Ralf Niemann, Jörg-Christian Porrmann, Mario Rückert, Ulrich Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Fürstenallee 11 33102 Paderborn Germany

ISBN: (纸本)9780387275574

Due to continuous advancements in modern technology processes which have resulted in integrated circuits with smaller feature sizes and higher complexity, current system-on-chip designs consist of many different components such as memories, interfaces and microprocessors. To handle this growing number of components, an efficient communication structure must be provided and incorporated during system design. This work deals with the implementation of an efficient communication structure for an on-chip multiprocessor design. The internal structure of one node is proposed and specified by its requirements. Furthermore, different routing strategies are implemented. Moreover, the communication structure is mapped on a standard cell process to examine the achieved processing speed and to determine the area requirements.

关键词： Network-on-chip

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Placement-oriented modeling of partially reconfigurable architectures

Placement-oriented modeling of partially reconfigurable arch...

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19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

作者： Koester, Markus Porrmann, Mario Rückert, Ulrich Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany

ISBN: (纸本)0769523129

Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. However, work on general approaches to model reconfigurable hardware is quite rare. Therefore, we have developed a new analytical model, which can be used for the analysis of the various approaches to dynamic reconfiguration. Based on our model we define metrics for partial reconfiguration to evaluate different system approaches. Our main objective is to analyze placement algorithms for partially reconfigurable architectures. The model is able to consider miscellaneous constraints and cost parameters for online placement. Thus, placement can be adapted to dynamically changing system environments.

关键词： Distributed computer systems

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Analytical approach to massively parallel architectures for nanotechnologies

Analytical approach to massively parallel architectures for ...

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IEEE 16th International Conference on Application-Specific systems, Architectures, and Processors, ASAP 2005

作者： Jäger, Björn Niemann, Jörg-Christian Rückert, Ulrich Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Germany

ISBN: (纸本)0769524079

In the emerging field of single-chip multiprocessors (CMP) analytical models of performance and power consumption are necessary for design space exploration and the analysis of existing architectures. In the light of ever decreasing structure sizes in microchips the scalability of proposed CMPs is of great interest to the developers. Looking even further into the future at the possibilities offered by, e. g., nanotechnology, a set of such models may help to identify promising architectures and possible bottlenecks even before the enabling technologies exist. In this paper, we present our current work in this area in the form of two models. The first and very basic model is based on Amdahl's law and gives a first promising outlook on chip multiprocessing. Based on the more complex BSP model our second model takes the on-chip communication into account and thus allows a much more detailed look at the architecture. In both cases, basic laws of circuit technology have been combined with the underlying models that now take the effects of device scaling into account. Later we will also present the GigaNetIC1 architecture, a CMP developed by our research group. It will then be analyzed by applying the BSP-based model. © 2005 IEEE.

关键词： Computer architecture

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CSD: Cell-based service discovery in large-scale robot networks

CSD: Cell-based service discovery in large-scale robot netwo...

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作者： Du, Jia Lei Witkowski, Ulf Rückert, Ulrich System and Circuit Technology Research Group Heinz Nixdorf Institute University of Paderborn 33102 Paderborn Germany

ISBN: (纸本)0780389123

If robots are deployed in large numbers in our environment in future, collaboration between the presumably specialized robots will be essential for a successful operation. The robots will set up mobile ad-hoc networks for communication and efficient routing and discovery protocols for such robot networks will provide the basic layer for a successful collaboration of the robots. In this paper we present a service discovery protocol that allows robots to efficiently discover available services in the network. It is specifically designed for large-scale robot networks. It takes into account the high dynamics of robot networks and exploits the position data of the robots to increase scalability and efficiency. A cellbased grid with master nodes in each cell forms the basic structure. Through proactive intra-cell communication and reactive inter-cell communication, scalability is ensured and the effects of node movements on the overall network are minimized. We implemented our solution in an example scenario. © 2005 IEEE.

关键词： Multipurpose robots

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