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检索条件"机构=Parallel & Distributed Processing Laboratory"

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Load scheduling: Reducing pressure on distributed register files for free

Load scheduling: Reducing pressure on distributed register f...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Wen, Mei Wu, Nan Guan, Maolin Zhang, Chunyuan National Laboratory for Parallel and Distributed Processing Chang Sha Hu Nan 410073 China

ISBN: (纸本)9781424419227

In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered VLIW processors with distributed register files while not increasing VLIW scheduling length. We have implemented load scheduling in compiler for Imagine and FT64 stream processors. The result shows that the proposed technique effectively reduces the number of variables spilled to memory, and can even eliminate it. The algorithm presented in this paper is extremely efficient in embedded processor with limited register resource because it can improve registers utilization instead of increasing the requirement for the number of registers. ©2008 IEEE.

关键词： Scheduling

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Jammer localization in wireless sensor networks

Jammer localization in wireless sensor networks

引用

5th International Conference on Wireless Communications, Networking and Mobile Computing, WiCOM 2009

作者： Yanqiang, Sun Xiaodong, Wang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424436934

Jamming style Denial-of-Service attack is the transmission of radio signals that disrupt communications by decreasing the signal to noise ratio. This kind of attack can be easily launched by jammer through either bypassing MAC-layer protocols or emitting a radio signal targeted at blocking a particular channel. In this paper, we consider the item of localizing a jammer in which little work has been done. First we explored the existing localization algorithms that have been used in wireless sensor networks. We then proposed a Geometry-Covering based Localization (GCL) algorithm, which utilizes the knowledge of computing geometry, especially the convex hull. Simulation results showed that GCL is able to achieve higher accuracy than Centroid Localization, and has the time complexity of O (nlogn) , which is proper to sensor networks. ©2009 IEEE.

关键词： Geometry

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HiAL-Ckpt: A hierarchical application-level checkpointing for CPU-GPU hybrid systems

HiAL-Ckpt: A hierarchical application-level checkpointing fo...

引用

International Conference on Computer Science and Education

作者： Xu, Xinhai Lin, Yufei Tang, Tao Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

In light of its powerful computing capacity and high energy efficiency, GPU (graphics processing unit) has become a focus in the research field of HPC (High Performance Computing). CPU-GPU heterogeneous parallel systems have become a new development trend of super-computer. However, the inherent unreliability of the GPU hardware deteriorates the reliability of super-computer. We have researched on the fault-tolerance(FT) technique for CPU-GPU heterogeneous parallel systems, and introduced a new checkpointing mechanism, i.e., the hierarchical application-level checkpointing, for such systems. The basic idea of this new checkpointing mechanism is checkpointing at two independent levels, i.e., CPU level and GPU level, to tolerate CPU and GPU faults respectively. Based on the idea, we have also designed and implemented a hierarchical application-level checkpointing tool "HiAL-Ckpt". Using this tool, programmers can insert two kinds of directives, i.e., CPU directives and GPU directives into a program, and the compiler will transform the directives into CPU or GPU checkpointing codes according to their nature. From the case study of SWIM, a test bench from spec2000 benchmark suite, we have demonstrated the validity of the hierarchical application-level checkpointing technique. The experimental results show that the falut-tolerance temporal cost of HiAL-Ckpt for SWIM is only 2.25%, compared with the executing time of SWIM without any FT work. ©2010 IEEE.

关键词： Graphics processing unit

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A full-pipelined architecture of the schnorr-euchner MIMO sphere decoder

引用

9th FTRA InternationalConference on Future Information Technology, FutureTech 2014

作者： Guo, Lei Zeng, Shirong Dou, Yong Jiang, Jingfei National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9783642550379

Multiple-input and multiple-output (MIMO) is an important approach in high-rate wireless communications. The Schnorr-Euchner (SE) sphere-decoding algorithm enables fast detection for receivers by recursive tree searching with optimized expanding order. In this paper, we propose a looped-pipeline architecture for an SE MIMO detector that processes multiple groups of data in parallel. The full-pipelined design has a short critical path that provides a maximum working frequency of 229 MHz on FPGA. High throughput is achieved at a relatively low cost. © 2014 Springer-Verlag Berlin Heidelberg.

关键词： Field programmable gate arrays (FPGA)

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MemHole: An efficient black-box approach to consolidate memory in virtualization platform

MemHole: An efficient black-box approach to consolidate memo...

引用

41st International Conference on parallel processing Workshops, ICPPW 2012

作者： Zhang, Pengfei Chu, Rui Wang, Huaimin National Laboratory for Parallel and Distributed Processing National University of Defense Technology United States

ISBN: (纸本)9780769547954

As an important aspect of the hardware resource consolidation in virtualization environment, memory consolidation and over-commitment has been motivated by the increasing elastic computing cloud platform. The most popular consolidation technology, Memory Balloon, might introduce serious performance penalty with thrashing when guest memory usage changes dramatically. In order to overcome the drawback of Memory Balloon and guarantee the system performance, we propose Mem Hole, which provides more guest physical memory than really allocated and makes the corresponding host physical mapping undetermined until accessed, to reduce the thrashing of guest memory paging. The prototype of Mem Hole has been implemented in Xen platform and the efficiency has been shown in the preliminary evaluation. © 2012 IEEE.

关键词： Virtualization

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Optimized deep belief networks on CUDA GPUs

Optimized deep belief networks on CUDA GPUs

引用

International Joint Conference on Neural Networks, IJCNN 2015

作者： Li, Teng Dou, Yong Jiang, Jingfei Wang, Yueqing Lv, Qi National Laboratory for Parallel and Distributed Processing National University of Defense and Technology Changsha China

ISBN: (纸本)9781479919604

A deep belief network (DBN) is an important branch of deep learning models and has been successfully applied in many machine learning and pattern recognition fields such as computer vision and speech recognition. However, the training of billions of parameters in DBN is computationally challenging for modern central processing units (CPUs). Many studies have reported the efficient implementations of the pre-training process of DBNs for graphics processing units (GPUs), but few studies have mentioned the fine-tuning process of DBNs. In this paper, we describe an efficient DBN implementation on the GPU, including the pre-training and fine-tuning processes. Experimental results show that our proposed method on the GPU (NVIDIA Tesla K40c) achieves up to 22 speedups on the pre-training process and 33 speedups on the fine-tuning processes compared with conventional CPU (Intel Core i7-4790K) implementations. Moreover, the performance of our algorithm is superior to that of the OpenBLAS library on the CPU and the CUBLAS library on the GPU. © 2015 IEEE.

关键词： Graphics processing unit

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Mapping OpenMP concepts to the stream programming model

Mapping OpenMP concepts to the stream programming model

引用

International Conference on Computer Science and Education

作者： Tang, Tao Lin, Yisong Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

OpenMP is a widely used parallel programming model on traditional multi-core processors. Generally, OpenMP is used to develop fine-grained parallelism through a multithread model. Stream programming model is a new kind of parallel programming model for stream architectures. OpenMP bears a resemblance to the stream programming model at some level. The transformation between the two models has attracted much attention from the research community, since it is the foundation of porting programs between the two architectures. Most related researches focus on the efficiency of porting existing parallel programs to the new architectures such as GPUs. Very few of these studies, however, focus on the portative problem systematically, namely, what kind of parallel programs can be or should be transplanted into stream programs and mapped to run on the stream processors. In this paper, we study the mapping relationship of parallel mechanism in OpenMP to the stream programming model, and point out those parallel mechanisms in OpenMP that are infeasible or undesirable for stream programs. By analyzing two typical benchmarks, we draw the conclusion that a majority of scientific applications are suitable to be mapped to the stream programming model. Our conclusion effectively validates the idea of accelerating scientific applications with the stream processors. ©2010 IEEE.

关键词： Mapping

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A stream system-on-chip architecture for high speed target recognition based on biologic vision

A stream system-on-chip architecture for high speed target r...

引用

12th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2007

作者： Wu, Nan Yang, Qianming Wen, Mei He, Yi Xun, Changqing Zhang, Chunyuan National Laboratory for Parallel and Distributed Processing Chang Sha Hu Nan 410073 China

ISBN: (纸本)9783540743088

For target recognition based on biologic vision, an application-specific stream SOC: MASA-MI is described in this paper. MASA-MI consists of several heterogeneous cores, and a stream accelerator core is used to accelerate matching image which consumes the most time in target recognition. We implemented it on Altera EP2S60 FPGA. Result shows the 166MHz MASA-MI provides a peak performance of 585 fps. MASA-MI's performance is an order of magnitude higher than those of today's DSPs such as the Texas Instruments TMS320DM642 (600MHz). On the other hand, the cost is far less than special purpose processors. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Integrated circuit layout

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An empirical study of reviewer recommendation in pull-based development model 17

An empirical study of reviewer recommendation in pull-based ...

引用

9th Asia-Pacific Symposium on Internetware, Internetware 2017

作者： Yang, Cheng Zhang, Xunhui Zeng, Lingbin Fan, Qiang Yin, Gang Wang, Huaimin National Laboratory for Parallel and Distributed Processing College of Computer Changsha Hunan410073 China

ISBN: (纸本)1595930361

Code review is an important process to reduce code defects and improve software quality. However, in social coding communities using the pull-based model, everyone can submit code changes, which increases the required code review efforts. Therefore, there is a great need of knowing the process of code review and analyzing the pre-existing reviewer recommendation algorithms. In this paper, we do an empirical study about the PRs and their reviewers in Rails project. Moreover, we reproduce a popular and effective IR-based code reviewer recommendation algorithm and validate it on our dataset which contains 16,049 *** find that the inactive reviewers are very important to code reviewing process, however, the pre-existing method's recommendation result strongly depends on the activeness of reviewers. © 2017 Association for Computing Machinery.

关键词： Codes (symbols)

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Factorization Machine-based Unsupervised Model Selection Method

Factorization Machine-based Unsupervised Model Selection Met...

引用

2022 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2022

作者： Zhang, Ruyi Wang, Yijie Xu, Hongzuo Zhou, Haifang National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory China

ISBN: (数字)9781665452588

ISBN: (纸本)9781665452588

Machine learning is broadly used in many intelligent cybernetic systems. With the burgeoning of the communities of AI, the number of machine learning-based models is rapidly increasing, but picking a suitable and optimal (or relatively good) model from overwhelming options has become a conundrum when deploying a new system. Therefore, we are motivated by an intriguing question: Can we automatically select a proper model for new data? However, unsupervised model selection poses two main challenges: (i) Evaluation and comparison of candidate models on the new data are infeasible due to the lack of labels;and (ii) It is non-trivial to build relationships between model performance and data characteristics when the interaction between these characteristics should be considered. In light of these limitations, this paper proposes a factorization machine-based unsupervised model selection method. Following mainstream model selection protocols, we also leverage model performance on prior known datasets. Differently, we learn higher-order complex relationships between model performance and dataset characteristics. Specifically, our method transfers the historical performance into a second-order function of meta-features and embedding weights by harnessing the power of factorization machine. This function can be subsequently used to select a proper model when given a new dataset. Extensive experiments show that our method obtains more superior model selection performance than five state-of-the-art approaches, and our method executes faster than its competitors by approximate three magnitudes. © 2022 IEEE.

关键词： Factorization

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