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Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

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Chinese Physics B 2016年第3期25卷 283-289页

作者：黄鹏程陈书明陈建军 College of Computer National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

关键词： floating body effect in-line stacking silicon-on-insulator source injection

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Simulation analysis of heavy-ion-induced single-event response for nanoscale bulk-Si FinFETs and conventional planar devices

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Science China(Technological Sciences) 2017年第3期60卷 459-466页

作者： YU JunTing CHEN ShuMing CHEN JianJun HUANG PengCheng College of Computer National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

FinFET technologies are becoming the mainstream process as technology scales *** on 28-nm bulk-Si FinFETs and

关键词： charge collection bipolar amplification reversed bipolar effect single-event effect(SEE) single-event transient(SET) FinFET planar device

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Speeding up the MATLAB complex networks package using graphic processors

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Chinese Physics B 2011年第9期20卷 460-467页

作者：张百达唐玉华吴俊杰李鑫 National laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Department of Computer Science and Technology School of ComputerNational University of Defense Technology

The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units （GPU）. This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3x. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

关键词： complex networks graphic processors unit MATLAB Jacket Toolbox

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Static Power Optimization for Homogeneous Multiple GPUs Based on Task Partition

Static Power Optimization for Homogeneous Multiple GPUs Base...

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2nd International Congress on Computer Applications and Computational Science (CACS 2011)

作者： Lin, Yisong Tang, Tao Wang, Guibin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9783642283079;9783642283086

Recently, GPU has been widely used in High Performance Computing (HPC). In order to improve computational performance, several GPUs are integrated into one computer node in practical system. However, power consumption of GPUs is very high and becomes as bottleneck to its further development. In doing so, optimizing power consumption have been draw broad attention in the research area and industry community. In this paper, we present an energy optimization model considering performance constraint for homogeneous multi-GPUs, and propose a performance prediction model when task partitioning policy is specified. Experiment results validate that the model can accurately predict the execution of program for single or multiple GPUs, and thus reduce static power consumption by the guide of task partition.

关键词： Electric power utilization

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Instance-Specific Algorithm Selection via Multi-Output Learning

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Tsinghua Science and Technology 2017年第2期22卷 210-217页

作者： Kai Chen Yong Dou Qi Lv Zhengfa Liang the National Laboratory for Parallel and Distributed Processing National University of Defense TechnologyChangsha 410037China the College of Computer National University of Defense TechnologyChangsha 410037China

Instance-specific algorithm selection technologies have been successfully used in many research fields,such as constraint satisfaction and planning. Researchers have been increasingly trying to model the potential relations between different candidate algorithms for the algorithm selection. In this study, we propose an instancespecific algorithm selection method based on multi-output learning, which can manage these relations more *** kinds of multi-output learning methods are used to predict the performances of the candidate algorithms：（1）multi-output regressor stacking;（2） multi-output extremely randomized trees; and（3） hybrid single-output and multioutput trees. The experimental results obtained using 11 SAT datasets and 5 Max SAT datasets indicate that our proposed methods can obtain a better performance over the state-of-the-art algorithm selection methods.

关键词： algorithm selection multi-output learning extremely randomized trees performance prediction constraint satisfaction

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A field-based service management and discovery method in multiple clouds context

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Frontiers of Computer Science 2019年第5期13卷 976-995页

作者： Shuai ZHANG Xinjun MAO Fu HOU Peini LIU College of Computer National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

In diverse and self-governed multiple clouds context, the service management and discovery are greatly challenged by the dynamic and evolving features of services. How to manage the features of cloud services and support accurate and efficient service discovery has becomean open problem in the area of cloud computing. This paper proposes a field model of multiple cloud services and corresponding service discovery method to address the issue. Different from existing researches, our approach is inspired by Bohr atom model. We use the abstraction of energy level and jumping mechanism to describe services status and variations, and thereby to support the service demarcation and discovery. The contributions of this paper are threefold. First, we propose the abstraction of service energy level to represent the status of services, and service jumping mechanism to investigate the dynamic and evolving features as the variations and re-demarcation of cloud services according to their energy levels. Second, we present user acceptable service region to describe the services satisfying users' requests and corresponding service discovery method, which can significantly decrease services search scope and improve the speed and precision of service discovery. Third, a series of algorithms are designed to implement the generation of field model, user acceptable service regions, service jumping mechanism, and user-oriented service discovery. We have conducted an extensive experiments on QWS dataset to validate and evaluate our proposed models and algorithms. The results show that field model can well support the representation of dynamic and evolving aspects of services in multiple clouds context and the algorithms can improve the accuracy and efficiency of service discovery.

关键词： service field service energy level service jumping service management service discovery multiple clouds

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SPICE modeling of memristors with multilevel resistance states

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Chinese Physics B 2012年第9期21卷 594-600页

作者：方旭东唐玉华吴俊杰 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Department of Computer Science and Technology School of ComputerNational University of Defense Technology

With CMOS technologies approaching the scaling ceiling, novel memory technologies have thrived in recent years, among which the memristor is a rather promising candidate for future resistive memory （RRAM）. Memristor＇s potential to store multiple bits of information as different resistance levels allows its application in multilevel cell （MCL） tech- nology, which can significantly increase the memory capacity. However, most existing memristor models are built for binary or continuous memristance switching. In this paper, we propose the simulation program with integrated circuits emphasis （SPICE） modeling of charge-controlled and flux-controlled memristors with multilevel resistance states based on the memristance versus state map. In our model, the memristance switches abruptly between neighboring resistance states. The proposed model allows users to easily set the number of the resistance levels as parameters, and provides the predictability of resistance switching time if the input current/voltage waveform is given. The functionality of our models has been validated in HSPICE. The models can be used in multilevel RRAM modeling as well as in artificial neural network simulations.

关键词： memristor multilevel cell SPICE model

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Betweenness-based algorithm for a partition scale-free graph

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Chinese Physics B 2011年第11期20卷 556-564页

作者：张百达吴俊杰唐玉华周静 National Laboratory for Parallel and Distributed Processing School of ComputersNational University of Defense Technology Department of Computer Science and Technology School of ComputersNational University of Defense Technology

Many real-world networks are found to be scale-free. However, graph partition technology, as a technology capable of parallel computing, performs poorly when scale-free graphs are provided. The reason for this is that traditional partitioning algorithms are designed for random networks and regular networks, rather than for scale-free networks. Multilevel graph-partitioning algorithms are currently considered to be the state of the art and are used extensively. In this paper, we analyse the reasons why traditional multilevel graph-partitioning algorithms perform poorly and present a new multilevel graph-partitioning paradigm, top down partitioning, which derives its name from the comparison with the traditional bottom-up partitioning. A new multilevel partitioning algorithm, named betweenness-based partitioning algorithm, is also presented as an implementation of top-down partitioning paradigm. An experimental evaluation of seven different real-world scale-free networks shows that the betweenness-based partitioning algorithm significantly outperforms the existing state-of-the-art approaches.

关键词： graph partitioning betweenness-based partitioning algorithm scale free network

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Scaling Internet services by LinuxDirector 4

Scaling Internet services by LinuxDirector

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4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

作者： Zhang, Wensong Jin, Shiyao Wu, Quanyuan National Laboratory for Parallel and Distributed Processing ChangshaHunan410073 China

ISBN: (纸本)0769505902

LinuxDirector is a software tool that directs network connections to multiple servers that share their workload, which can be used to build highly scalable and highly available services. LinuxDirector extends the TCP/IP stack of the Linux kernel to support three IP load balancing techniques, which can make parallel services of different kinds of server clusters to appear as a service on a single IP address. Four scheduling algorithms have been implemented to assign connections to different servers, and a simple distributed lock manager is provided for applications on different servers to access shared data consistently. Scalability is achieved by transparently adding or removing a node in the cluster and high availability is provided by detecting node or daemon failures and reconfiguring the system appropriately. This paper describes the design and implementation of LinuxDirector and presents several of its features including scalability, high availability, connection affinity and icmp handling. © 2000 IEEE.

关键词： Scalability

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FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing 10

FPGA accelerating double/quad-double high precision floating...

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24th ACM International Conference on Supercomputing, ICS'10

作者： Dou, Yong Lei, Yuanwu Wu, Guiming Guo, Song Zhou, Jie Shen, Li National Laboratory for Parallel and Distributed Processing NUDT Changsha 410073 China

ISBN: (纸本)9781450300186

In this paper we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on 128-bit or even 256-bit floating-point number representation. This paper addresses the accuracy when performing LU decomposition on large-scale matrices. In future ExaScale computing environments, accuracy errors are expected to increase up to a level which leaves only 11 significant bits in the mantissa. This is caused by the required large amount of accumulation operations which are in the order of O(n 3). Using exact long fixed-point numbers instead of usual floatingpoint numbers in the accumulation process, leads to exact accumulation results with only one bit error, originated by the rounding in the last normalization step. We have developed two types of High Precision Multiplication and Accumulation (HP-MAC), for Double-Double (128 bits) and Quad-Double (256 bits) floating-point, respectively, and implemented them into FPGA devices. We propose a two-level RAM banks scheme to store and add long fixed-point numbers with minimized crucial data paths lengths. We also introduce a scheme of partial summation to enhance the pipeline throughput of MAC operations, by dividing the summation function into 4 partial operations, processed in 4 banks. To prove the concept, we prototyped six 128-bit HP-MAC units into a Xilinx Virtex-5 XC5VLX330 FPGA chip and performed LU decomposition. The experimental results show accuracy improvement of 10 to 24 bits, compared to a software approach with similar precision arithmetic. Moreover, our LU decomposition implementation, based on FPGA running at 133MHz, achieves 29X - 56X better performance and much lower power consumption compared to the use of a software-based library running on an Intel Core2 Quad Q8200 CPU at 2.33GHz. © 2010 ACM.

关键词： Field programmable gate arrays (FPGA)

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