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Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

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Chinese Physics B 2016年第4期25卷 495-500页

作者：于俊庭陈书明陈建军黄鹏程宋睿强 College of Computer National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor （FinFET） technology. However, the studies of charge sharing induced single-event transient （SET） pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design （3DTCAD） mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing （RBB）, the circuit with forward body-biasing （FBB） is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.

关键词： body-biasing SET pulse quenching charge sharing bulk FinFET process

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Weakly hard real-time scheduling algorithm for multimedia embedded system on multiprocessor platform

Weakly hard real-time scheduling algorithm for multimedia em...

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2008 the 1st IEEE International Conference on Ubi-Media Computing and Workshops, U-Media2008

作者： Wu, Tong Jin, Shiyao National Laboratory of Parallel and Distributed Processing NUDT Changsha Hunan China

ISBN: (纸本)9781424418657

Multiprocessor architectures are becoming more attractive for embedded systems, and also for multimedia embedded systems. In multimedia embedded systems, there exist both hard real-time tasks and multimedia stream with QoS guarantee. In this context, researched on integrated schedule of both hard real-time tasks and streams are urgent affairs. This paper analyzes the shortcomings of the current approach - multimedia server, and then based on the DBF algorithm, proposes an algorithm which also considers the resource constraint. According to the different budget schemes, greedy algorithm and optimistic algorithm are brought up. Results show the performance of the algorithms. © 2008 IEEE.

关键词： Embedded systems

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Uml based statistical testing acceleration of distributed safety-critical software

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2nd International Symposium on parallel and distributed processing and Applications, ISPA 2004

作者： Yan, Jiong Wang, Ji Chen, Huo-Wang National Laboratory for Parallel and Distributed Processing Changsha China

ISBN: (纸本)9783540241287

It is necessary to assess the reliability of distributed safety-critical systems to a high degree of confidence before they are deployed in the field. However, distributed safety-critical software systems often include some rarely executed critical functions that are often inadequately tested in statistical testing based reliability estimation. This paper presents a method that can accelerate statistical testing of distributed safety-critical software. The method starts with the derivation of scenario usage diagram model (SUD) from UML diagrams annotated with usage related attributes and reliability attributes. Then the statistical testing accelerating method based on importance sampling is presented. When both the critical scenarios and the entire software are adequately tested, the method can still compute the unbiased software reliability from the test results with much less test cases. Thus, the statistical testing cost of distributed safety-critical software can be reduced effectively. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Software reliability

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Optimizing guest swapping using elastic and transparent memory provisioning on virtualization platform

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Frontiers of Computer Science 2016年第5期10卷 908-924页

作者： Xi LI Pengfei ZHANG Rui CHU Huaimin WANG School of Information Science and Engineering Central South University Changsha 410083 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410008 China

On virtualization platforms, peak memory de- mand caused by hotspot applications often triggers page swapping in guest OS, causing performance degradation in- side and outside of this virtual machine （VM）. Even though host holds sufficient memory pages, guest OS is unable to utilize free pages in host directly due to the semantic gap between virtual machine monitor （MM） and guest operat- ing system （OS）. Our work aims at utilizing the free memory scattered in multiple hosts in a virtualization environment to improve the performance of guest swapping in a transparent and implicit way. Based on the insightful analysis of behav- ioral characteristics of guest swapping, we design and im- plement a distributed and scalable framework HybridSwap. It dynamically constructs virtual swap pools using various policies, and builds up a synthetic swapping mechanism in a peer-to-peer way, which can adaptively choose different vir- tual swap pools. We implement the prototype of HybridSwap and evaluate it with some benchmarks in different scenar- ios. The evaluation results demonstrate that our solution has the ability to promote the guest swapping efficiency indeed and shows a double performance promotion in some cases. Even in the worst case, the system overhead brought by Hy- bridSwap is acceptable.

关键词： virtualization memory management guestswapping performance degradation

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Chinese named rntity recognition with a hybrid-statistical model

Chinese named rntity recognition with a hybrid-statistical m...

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7th Asia-Pacific Web Conference on Web Technologies Research and Development - APWeb 2005

作者： Zhang, Xiaoyan Wang, Ting Tang, Jintao Zhou, Huiping Chen, Huowang National Laboratory for Parallel and Distributed Processing Changsha Hunan 410073 China

With the rapid growth of the available information on the Internet, it is more difficult for us to find the relevant information quickly on the Web. Named Entity Recognition (NER), one of the key techniques in some web information processing tools such as information retrieval and information extraction, has been paid more and more attention. In this paper we address the problem of Chinese NER using a hybrid-statistical model. This study is concentrated on entity names (personal names, location names and organization names), temporal expressions (dates and times) and number expressions. The method is characterized as follows: firstly, NER and Part-of-Speech tagging have been integrated into a unified framework;secondly, it combines Hidden Markov Model (HMM) with Maximum Entropy Model (MEM) by taking MEM as a sub-model invoked in Viterbi algorithm;thirdly, the Part-of-Speech information of the context has been used in MEM. The experiment shows that the hybrid-statistical model could achieve preferable results of Chinese NER, in which the F1 value ranges from 74% to 92% for all kinds of named entities on an open-test data. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Pattern recognition

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MilkyWay-2 supercomputer： system and application

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Frontiers of Computer Science 2014年第3期8卷 345-356页

作者： Xiangke LIAO Liquan XIAO Canqun YANG Yutong LU Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

On June 17, 2013, MilkyWay-2 （Tianhe-2） supercomputer was crowned as the fastest supercomputer in the world on the 41th TOP500 list. This paper provides an overview of the MilkyWay-2 project and describes the design of hardware and software systems. The key architecture features of MilkyWay-2 are highlighted, including neo-heterogeneous compute nodes integrating commodity- off-the-shelf processors and accelerators that share similar instruction set architecture, powerful networks that employ proprietary interconnection chips to support the massively parallel message-passing communications, proprietary 16- core processor designed for scientific computing, efficient software stacks that provide high performance file system, emerging programming model for heterogeneous systems, and intelligent system administration. We perform extensive evaluation with wide-ranging applications from LINPACK and Graph500 benchmarks to massively parallel software deployed in the system.

关键词： MilkyWay-2 supercomputer petaflops computing neo-heterogeneous architecture interconnect network heterogeneous programing model system management benchmark optimization performance evaluation

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FPQRNA: Hardware-accelerated qrna package for noncoding rna gene detecting on FPGA

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Journal of Bioinformatics and Computational Biology 2010年第4期8卷 743-761页

作者： Xia, Fei Dou, Yong Lei, Guo-Qing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

Noncoding RNAs (ncRNAs) have important functional roles in biological processes and have become a central research interest in modern molecular biology. However, how to find ncRNA attracts much more attention since ncRNA gene sequences do not have strong statistical signals, unlike protein coding genes. QRNA is a powerful program and has been widely used as an efficient analysis tool to detect ncRNA gene at present. Unfortunately, the O(L ³) computing requirements and complicated data dependency greatly limit the usefulness of QRNA package with the explosion in gene database. In this paper, we present a fine-grained parallel QRNA prototype system, FPQRNA, for accelerating ncRNA gene detection application on FPGA chip. We propose a systolic-like array architecture with multiple PEs (processing Elements). We partition the tasks by columns and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load matrices from external memory. The experimental results show a speedup factor of more than 18× over the QRNA - 2.0.3c software running on a PC platform with AMD Phenom 9650 Quad CPU for pairwise sequence alignment with 996 residues, however the power consumption of our FPGA accelerator is only about 30% of that of the general-purpose microprocessors. © 2010 Imperial College Press.

关键词： Bioinformatics fine-grained parallelism FPGA hardware accelerator noncoding RNA

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Mirror image:newfangled cell-level layout technique for single-event transient mitigation

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Chinese Science Bulletin 2014年第23期59卷 2850-2858页

作者： Pengcheng Huang Shuming Chen Zhengfa Liang Jianjun Chen Chunmei Hu Yibai He Micro-electronics and Microprocessor Institute National University of Defense Technology National Laboratory for Parallel and Distributed Processing National University of Defense Technology

Recent years,the hardening of combinational circuits is becoming a common *** the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)*** mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.

关键词：单事件技术细胞瞬态镜像组合逻辑电路次布 CMOS工艺

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The TH Express high performance interconnect networks

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Frontiers of Computer Science 2014年第3期8卷 357-366页

作者： Zhengbin PANG Min XIE Jun ZHANG Yi ZHENG Guibin WANG Dezun DONG Guang SUO Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

Interconnection network plays an important role in scalable high performance computer （HPC） systems. The TH Express-2 interconnect has been used in MilkyWay-2 system to provide high-bandwidth and low-latency interprocessot communications, and continuous efforts are devoted to the development of our proprietary interconnect. This paper describes the state-of-the-art of our proprietary interconnect, especially emphasizing on the design of network interface. Several key features are introduced, such as user-level communication, remote direct memory access, offload collective operation, and hardware reliable end-to-end communication, etc. The design of a low level message passing infrastructures and an upper message passing services are also proposed. The preliminary performance results demonstrate the efficiency of the TH interconnect interface.

关键词： HPC network interface chip （NIC） TH Express nterconnect offload collective operation

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Towards estimating expected sizes of probabilistic skylines

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Science China(Information Sciences) 2011年第12期54卷 2574-2584页

作者： YANG YongTao & WANG YiJie National Key laboratory for parallel and distributed processing, School of Computer, National University of Defense Technology, Changsha 410073, China 1. National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

We consider the maximal vector problem on uncertain data, which has been recently posed by the study on processing skyline queries over a probabilistic data stream in the database context. Let D n be a set of n points in a d-dimensional space and q (0 < q 1) be a probability threshold; each point in D n has a probability to occur. Our problem is concerned with how to estimate the expected size of the probabilistic skyline, which consists of all the points that are not dominated by any other point in D n with a probability not less than q. We prove that the upper bound of the expected size is O(min{n, (- ln q)(ln n) d-1 }) under the assumptions that the value distribution on each dimension is independent and the values of the points along each dimension are distinct. The main idea of our proof is to find a recurrence about the expected size and solve it. Our results reveal the relationship between the probability threshold q and the expected size of the probabilistic skyline, and show that the upper bound is poly-logarithmic when q is not extremely small.

关键词： probabilistic skyline probabilistic data streams expected size

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