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Internet-based virtual computing environment(iVCE):Concepts and architecture

Science in China(Series F) 2006年第6期49卷 681-701页

作者： LU Xicheng WANG Huaimin WANG Ji National Laboratory for Parallel and Distributed Processing Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

Resources over Internet have such intrinsic characteristics as growth, autonomy and diversity, which have brought many challenges to the efficient sharing and comprehensive utilization of these resources. This paper presents a novel approach for the construction of the Internet-based Virtual Computing Environment （iVCE）, whose sig- nificant mechanisms are on-demand aggregation and autonomic collaboration. The iVCE is built on the open infrastructure of the Internet and provides harmonious, transparent and integrated services for end-users and applications. The concept of iVCE is presented and its architectural framework is described by introducing three core concepts, i.e., autonomic element, virtual commonwealth and virtual executor. Then the connotations, functions and related key technologies of each components of the architecture are deeply analyzed with a case study, iVCE for Memory.

关键词： resource aggregation collaboration virtual computing environment Internet

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CWLP:coordinated warp scheduling and locality-protected cache allocation on GPUs

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Frontiers of Information Technology & Electronic Engineering 2018年第2期19卷 206-220页

作者： Yang ZHANG Zuo-cheng XING Cang LIU Chuan TANG National Laboratory for Parallel and Distributed Processing National University of Defense Technology

As we approach the exascale era in supercomputing, designing a balanced computer system with a powerful computing ability and low power requirements has becoming increasingly important. The graphics processing unit（GPU） is an accelerator used widely in most of recent supercomputers. It adopts a large number of threads to hide a long latency with a high energy efficiency. In contrast to their powerful computing ability, GPUs have only a few megabytes of fast on-chip memory storage per streaming multiprocessor（SM）. The GPU cache is inefficient due to a mismatch between the throughput-oriented execution model and cache hierarchy design. At the same time, current GPUs fail to handle burst-mode long-access latency due to GPU＇s poor warp scheduling ***, benefits of GPU＇s high computing ability are reduced dramatically by the poor cache management and warp scheduling methods, which limit the system performance and energy efficiency. In this paper, we put forward a coordinated warp scheduling and locality-protected（CWLP） cache allocation scheme to make full use of data locality and hide latency. We first present a locality-protected cache allocation method based on the instruction program counter（LPC） to promote cache performance. Specifically, we use a PC-based locality detector to collect the reuse information of each cache line and employ a prioritised cache allocation unit（PCAU） which coordinates the data reuse information with the time-stamp information to evict the lines with the least reuse possibility. Moreover, the locality information is used by the warp scheduler to create an intelligent warp reordering scheme to capture locality and hide latency. Simulation results show that CWLP provides a speedup up to 19.8% and an average improvement of 8.8% over the baseline methods.

关键词： Locality Graphics processing unit （GPU） Cache allocation Warp scheduling

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Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits

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Science China(Information Sciences) 2015年第2期58卷 165-173页

作者： HUANG PengCheng CHEN ShuMing CHEN JianJun WU ZhenYu LIANG ZhengFa HU ChunMei LIANG Bin LIU BiWei Micro-electronics and Microprocessor Institute College of Computer ScienceNational University of Defense Technology National Laboratory for Parallel and Distributed Processing College of Computer ScienceNational University of Defense Technology

The advancement in the process leads to more concern about the Single Event(SE) sensitivity of the Differential Cascade Voltage Switch Logic(DCVSL) circuits. The simulation results indicate that the Single Event Transient(SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated.

关键词： differential cascade voltage switch logic(DCVSL) single event transient(SET) effective collection time pulse feedback feature(PFF) across-coupled structure

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Providing Virtual Cloud for Special Purposes on Demand in JointCloud Computing Environment

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Journal of Computer Science & Technology 2017年第2期32卷 211-218页

作者： Dong-Gang Cao Member, CCF, IEEE, Bo An Pei-Chang Shi Huai-Min Wang Key Laboratory of High Confidence Software Technologies (Peking University) Ministry of Education Beijing 100871 China National Key Laboratory for Parallel and Distributed Processing National University of Defense and Technology Changsha 410073 China

Cloud computing has been widely adopted by enterprises because of its on-demand and elastic resource usage paradigm. Currently most cloud applications are running on one single cloud. However, more and more applications demand to run across several clouds to satisfy the requirements like best cost efficiency, avoidance of vender lock-in, and geolocation sensitive service. JointCloud computing is a new research initiated by Chinese institutes to address the computing issues concerned with multiple clouds. In JointCloud, users＇ diverse and dynamic requirements on cloud resources axe satisfied by providing users virtual cloud （VC） for special purposes. A virtual cloud for special purposes is in essence a user＇s specific cloud working environment having the customized software stacks, configurations and computing resources readily available. This paper first introduces what is JointCloud computing and then describes the design rationales, motivation examples, mechanisms and enabling technologies of VC in JointCloud.

关键词： cloud computing JointCloud virtual cloud （VC） cloud working environment

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PartialRC: A Partial Recomputing Method for Efficient Fault Recovery on GPGPUs

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Journal of Computer Science & Technology 2012年第2期27卷 240-255页

作者：徐新海杨学军薛京灵林宇斐林一松 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer in the TOP500 list, built at NUDT （National University of Defense Technology） last year. However, despite their performance advantages, GPGPUs do not provide built-in fault-tolerant mechanisms to offer reliability guarantees required by many HPC applications. By analyzing the SIMT （single-instruction, multiple-thread） characteristics of programs running on GPGPUs, we have developed PartialRC, a new checkpoint-based compiler-directed partial recomputing method, for achieving efficient fault recovery by leveraging the phenomenal computing power of GPGPUs. In this paper, we introduce our PartialRC method that recovers from errors detected in a code region by partially re-computing the region, describe a checkpoint-based faulttolerance framework developed on PartialRC, and discuss an implementation on the CUDA platform. Validation using a range of representative CUDA programs on NVIDIA GPGPUs against FullRC （a traditional full-recomputing Checkpoint-Rollback-Restart fault recovery method for CPUs） shows that PartialRC reduces significantly the fault recovery overheads incurred by FullRC, by 73.5% when errors occur earlier during execution and 74.6% when errors occur later on average. In addition, PartialRC also reduces error detection overheads incurred by FullRC during fault recovery while incurring negligible performance overheads when no fault happens.

关键词： GPGPU partial recomputing fault tolerance CUDA checkpointing

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Memory access characterization of scientific applications on GPU and its implication on low power optimization

Memory access characterization of scientific applications on...

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2011 International Conference on Computational and Information Sciences, ICCIS 2011

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9780769545011

Following current IC design technology trend, modern GPUs integrate more and more processing cores, and the speed gap between processor and memory system becomes even larger. As the number of cores continually increases, the available bandwidth per core decreases correspondingly. Therefore, memory access performance has been one of the most critical bottlenecks for better performance. This paper analyzes the impact of memory system on performance and scalability for GPU with several scientific applications using a cycle-accurate simulator. Two observations we make are (1) that memory bandwidth has relatively greater impact on performance than memory latency, because the latter factor could be well hidden with tremendous concurrent executing threads supported in modern GPU architecture, and (2) that through examining the performance scalability of variable active cores, using the maximum hardware-supported cores may not bring in better performance, especially for the memory-intensive applications. In the end we suggest a better power-efficient exploitation of GPU is to make judicious concurrency-throttling based on the memory usage in application. © 2011 IEEE.

关键词： Graphics processing unit

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Data parallelism exploiting for H.264 encoder

Data parallelism exploiting for H.264 encoder

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International Conference on Multimedia and Signal processing

作者： Wen, Mei Ren, Ju Wu, Nan Su, Huayou Xun, Changqing Zhang, Chunyuan Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9780769543567

Real-time H.264 encoding of high-definition (HD) video (up to 1080p) is a challenge workload to most existing programmable processors. Instead, the novel programmable parallel processors such as stream processor, Graphic processor unit (GPU) and DSP offer a different and very promising technology for these demands. Thus, parallel computing for H.264 encoding on these processors is becoming a hot research point. It's challenged, because most emerging parallel processors focus on supporting Data Level parallel (DLP), while the dependency inherently existing in traditional H.264 encoding algorithm significantly restricts exploiting DLP. Facing the challenge, this paper presents data parallel processing methods for key modules of H.264 encoder which can eliminate the dependency restriction. The result shows that key modules including Intra-prediction, Inter-prediction and CAVLC achieve significant speedup on stream processor by using these data parallel processing methods.© 2011 IEEE.

关键词： parallel processing systems

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Approximate Iteration Detection and Precoding in Massive MIMO

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China Communications 2018年第5期15卷 183-196页

作者： Chuan Tang Yerong Tao Yancang Chen Cang Liu Luechao Yuan Zuocheng Xing Luoyang Electronic Equipment Test Center LuoYang 471000China National Laboratory for Parallel and Distributed Processing National University of Defense TechnologyChangsha 410073China

Massive multiple-input multiple-output provides improved energy efficiency and spectral efficiency in 5 G. However it requires large-scale matrix computation with tremendous complexity, especially for data detection and precoding. Recently, many detection and precoding methods were proposed using approximate iteration methods, which meet the demand of precision with low complexity. In this paper, we compare these approximate iteration methods in precision and complexity, and then improve these methods with iteration refinement at the cost of little complexity and no extra hardware resource. By derivation, our proposal is a combination of three approximate iteration methods in essence and provides remarkable precision improvement on desired vectors. The results show that our proposal provides 27%-83% normalized mean-squared error improvement of the detection symbol vector and precoding symbol vector. Moreover, we find the bit-error rate is mainly controlled by soft-input soft-output Viterbi decoding when using approximate iteration methods. Further, only considering the effect on soft-input soft-output Viterbi decoding, the simulation results show that using a rough estimation for the filter matrix of minimum mean square error detection to calculating log-likelihood ratio could provideenough good bit-error rate performance, especially when the ratio of base station antennas number and the users number is not too large.

关键词： massive MIMO detection and precoding matrix inversion iteration refinement soft Viterbi decoding

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The design of QoS management framework based on CORBA A/V STREAM architecture 4

The design of QoS management framework based on CORBA A/V ST...

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4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

作者： Chen, Xiaomei Lu, Xichen Wang, Huaimin National Laboratory of Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)0769505902

As distributed multimedia applications become more widely diffused, flexibility for QoS management is increasingly essential. We put forward a QoS management framework called QoSMF. In order to solve the heterogeneous problems and get more flexible and reusable characteristics, we implement the QoSMF model into the CORBA A/V STREAM architecture. With the QoSMF, we can easily change the QoS strategies and arithmetic without wholly reprogramming and redesigning for different types of applications. © 2000 IEEE.

关键词： Common object request broker architecture (CORBA)

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Communication-aware task partition and voltage scaling for energy minimization on heterogeneous parallel systems

Communication-aware task partition and voltage scaling for e...

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2011 12th International Conference on parallel and distributed Computing, Applications and Technologies, PDCAT 2011

作者： Wang, Guibin Song, Wei National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9780769545646

Heterogeneous parallel systems have become popular in general purpose computing and even high performance computing fields. There are many studies focused on harnessing heterogeneous parallel processing for better performance. However the energy optimization for heterogeneous system has not been well studied. Owing to the differences in performance and energy consumption, the energy optimization technique for heterogeneous system is different from the existing methods designed for homogeneous system. Besides typical voltage scaling method, reasonable task partitioning is also an essential method for optimizing energy consumption on heterogeneous systems. Through partitioning a data parallel task and mapping sub-tasks onto several processors, one could achieve better performance and reduced energy consumption. As the computation cost reduces with specific accelerators, the communication overhead becomes more prominent. Therefore, the task partition optimization should holistically consider the computation improvement and communication overhead to achieve higher energy efficiency. Typically, task partition and voltage scaling are not orthogonal and influence the effect of each other in the energy optimization problem. In order to harness both two knobs efficiently, this paper proposes an integer linear programming (ILP) based energy-optimal solution designed for heterogeneous system. We present a case study of optimizing MGRID benchmark on a typical CPU-GPU heterogeneous system. The experimental results demonstrate that the proposed method could exploit the heterogeneity in different processors and achieve improved energy efficiency. © 2011 IEEE.

关键词： Energy efficiency

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