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IEEE International Conference on Microelectronic Systems Education

作者： J.E. Stine J. Grad I. Castellanos J. Blank V. Dave M. Prakash N. Iliev N. Jachimiec VLSI Computer Architecture Arithmetic and CAD Research Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.

关键词： High level synthesis System-on-a-chip CMOS technology Delay estimation Libraries Energy management Very large scale integration Educational programs Hardware Circuits

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Journal of Information Science and engineering: Editorial notice

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Journal of Information Science and engineering 2005年第5期21卷 i-ii页

作者： Lee, Der-Tsai Amato, Nancy M. Chang, Shih-Fu Chen, Homer H. Chen, Tsuhan Hsu, Tsan-Sheng Hwang, Jenq-Neng Kuo, Sy-Yen Kuo, Tei-Wei Li, Chung-Sheng Tokuyama, Takeshi Wing, Jeannette Wu, Tzong-Chen Yen, John Computer Science at Texas A and M University United States Parasol Laboratory United States IEEE Transactions on Parallel and Distributed Systems Computing Research Association's Committee on the Status of Women in Computing Research CRA-W's Distributed Mentor Program United States Department of Electrical Engineering Columbia University United States Lab. United States College of Electrical Engineering and Computer Science National Taiwan University Taiwan IEEE Transactions on Circuits and Systems for Video Technology IEEE Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA United States ACM ACM SIGACT IEEE Computer Society IICM Austria Research and Development of the Department Multimedia Signal Processing Technical Committee IEEE Signal Processing Society United States IEEE Transactions on Circuits and systems for Video Technology College of Electrical Engineering and Computer Science National Taiwan Ocean University Keelung Taiwan Department of Electrical Engineering National Taiwan University Taiwan Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan IEEE Technical Committee on Real-Time Systems Computer Science Division IBM T.J. Watson Research Center United States IBM Research Division Graduate School of Information Sciences Tohoku University Japan ACM IPSJ Mathematical Society of Japan Japan Department of Computer Science Computer Science Department Carnegie Mellon University United States National Academies of Science's Computer Science and Telecommunications Board United States Microsoft's Trustworthy Academic Advisory Board Intel Research Pittsburgh's Advisory Board United States Dartmouth's Institute for Security Technology Studies Advisory Committee Canada Sloan Research Fellowships Program Committee United States ACM Taiwan China Information Sciences and Technology Pennsylvania State University United States Laboratory for Intelligent Agents Penn State's School of Info

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Arches: an infrastructure for PSE development

Arches: an infrastructure for PSE development

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International Workshop on High-Level parallel Programming Models and Supportive Environments

作者： N. DeBardeleben W.B. Ligon R. Sass Parallel Architecture Research Laboratory Holcombe Department of Electrical & Computer Engineering Clemson University Clemson SC USA

In this paper, we describe Arches, an object-oriented framework for building domain-specific PSEs. The framework was designed to support a wide range of problem domains and to be extendable in a way that allows it to target very different high-performance computing models. To demonstrate this flexibility we describe two PSEs that have been developed from the same framework yet solve different problems and target very different computing platforms. The Coven PSE supports parallel applications that need the large-scale parallelism that is found in cost-effective Beowulf clusters. In contrast, the RCADE PSE targets reconfigurable computing (FPGA-based) platforms with fine-grain parallelism. RCADE was designed to aid NASA Earth scientists interested in studying satellite instrument data and who are unlikely to be schooled in low-level hardware design.

关键词： parallel processing Buildings Object oriented modeling Large-scale systems Concurrent computing NASA Earth Satellites Instruments Educational institutions

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Bandwidth-aware co-allocating meta-schedulers for mini-grid architectures

Bandwidth-aware co-allocating meta-schedulers for mini-grid ...

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IEEE International Conference on Cluster Computing

作者： W.M. Jones L.W. Pang W.B. Ligon D. Stanzione Parallel Architecture Research Laboratory Department of Electrical and Computer Engineering Clemson University Clemson SC USA Division of Graduate Education National Science Foundation Arlington VA USA

The interaction of simultaneously co-allocated jobs can often create contention in the network infrastructure of a dedicated computational grid. This contention can lead to degraded job run-time performance. We present several bandwidth-aware co-allocating meta-schedulers. These schedulers take into account inter-cluster network utilization as a means by which to mitigate this impact. We make use of a bandwidth-centric parallel job communication model that captures the time-varying utilization of shared inter-cluster network resources. By doing so, we are able to evaluate the performance of grid scheduling algorithms that focus not only on node resource allocation, but also on shared inter-cluster network bandwidth.

关键词： Resource management Bandwidth Switches Processor scheduling computer architecture computer networks Grid computing Laboratories computer science education Degradation

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parallel programmable finite field GF (2/sup m/) multipliers

Parallel programmable finite field GF (2/sup m/) multipliers

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IEEE computer Society Annual Symposium on VLSI

作者： N. Iliev J.E. Stine N. Jachimiec VLSI Computer Architecture Arithmetic and CAD Research Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL USA

Block (cyclic) channel coding standards for third generation cellular networks require the implementation of high-performance burst-error detection and correction algorithms. Galois field (GF) arithmetic is commonly used in this architecture for encoding and decoding error codes, however, many architectures still do not support dedicated functional units. This paper presents the design of a generic parallel finite-field GF (2/sup m/) multiplier targeted at DSP and embedded processors. As opposed to previous research, this design has the ability to utilize different primitive polynomials as an input, thereby, being able to be programmable. Moreover, a design is presented that is a combined binary and finite-field GF (2/sup m/) multiplier. Area, delay, and power dissipation results are presented from several ASIC libraries.

关键词： Galois fields Channel coding Land mobile radio cellular systems Arithmetic Decoding Digital signal processing Polynomials Delay Power dissipation Application specific integrated circuits

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Sequential and parallel Meta-Heuristics for Solving the Single Row Routing Problem

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Cluster Computing 2004年第2期7卷 123-139页

作者： Zomaya, Albert Y. Patterson, Daniel Olariu, Stephan School of Information Technologies The University of Sydney Sydney Australia Parallel Computing Research Laboratory Department of Electrical and Electronic Engineering The University of Western Australia Australia Department of Computer Science Old Dominion University Norfolk USA

The design of multi-layer printed circuit boards is vital in the construction of complex electronic systems. Wire routing is a crucial step in the overall design process, which can be decomposed into a number of single row routing (SRR) problems. This paper proposes an approach to solve the SRR problem based on parallel meta-heuristics. The development of this technique involves the design of an encoding strategy that allows all possible routings to be uniquely represented and the derivation of cost functions that maximizes the quality of the developed solutions. Further, parallelization of the proposed approach is attempted to improve the computational efficiency. The different stages of the development are backed by experiments to show the pros and cons of the sequential and parallel implementations.

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Job communication characterization and its impact on meta-scheduling co-allocated jobs in a mini-grid

Job communication characterization and its impact on meta-sc...

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： W.M. Jones L.W. Pang D. Stanzione W.B. Ligon Parallel Architecture Research Lab Department of Electrical and Computer Engineering Clemson University Clemson SC USA Division of Graduate Education National Science Foundation Arlington VA USA

Summary form only given. We present a bandwidth-centric parallel job communication model that takes into account inter-cluster network utilization as a means by which to capture the interaction and impact of simultaneously co-allocated jobs in a mini-grid. Our model captures the time-varying utilization of shared inter-cluster network resources in the grid. We compare our dynamic model with previous research that utilizes a fixed execution time penalty for co-allocated jobs. We have found that the fixed penalty model is more generous in its prediction of job turnaround time than our dynamic communication model. Additionally, we see that the penalty co-allocated jobs may experience without causing a severe performance degradation decreases as the number of clusters increases.

关键词： Grid computing Bandwidth Concurrent computing Predictive models Laboratories Processor scheduling Distributed computing parallel architectures computer science education Degradation

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On the performance of the POSIX I/O interface to PVFS

On the performance of the POSIX I/O interface to PVFS

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Euromicro Conference on parallel, Distributed and Network-Based Processing

作者： Murali Vilayannur R.B. Ross P.H. Carns Rajeev Thakur Anand Sivasubramaniam M. Kandemir Department of Computer Science and Engineering Pennsylvania State University University Park PA USA Argonne National Laboratory Argonne IL USA Parallel Architecture Research Laboratory Clemson University Clemson SC USA

The ever-increasing gap in performance between CPU/memory technologies and the I/O subsystem (disks, I/O buses) in modern workstations has exacerbated the I/O bottlenecks inherent in applications that access large disk resident data sets. A common technique to alleviate the I/O bottlenecks on clusters of workstations, is the use of parallel file systems. One such parallel file system is the parallel virtual file system (PVFS), which is a freely available tool to achieve high-performance I/O on Linux-based clusters. Here, we describe the performance and scalability of the UNIX I/O interface to PVFS. To illustrate the performance, we present experimental results using Bonnie++, a commonly used file system benchmark to test file system throughput; a synthetic parallel I/O application for calculating aggregate read and write bandwidths; and a synthetic benchmark which calculates the time taken to untar the Linux kernel source tree to measure performance of a large number of small file operations. We obtained aggregate read and write bandwidths as high as 550 MB/s with a Myrinet-based network and 160MB/s with fast Ethernet.

关键词： File systems Workstations Benchmark testing Aggregates Bandwidth Scalability System testing Throughput Linux Kernel

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Reconfigurable mapping functions for online architectures

Reconfigurable mapping functions for online architectures

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International parallel and Distributed Processing Symposium, IPDPS 2003

作者： Harinath, Shyamnath Sass, Ron Parallel Architecture Research Lab Holcombe Department of Electrical and Computer Engineering Clemson University 105 Riggs Hall ClemsonSC29634-0915 United States

ISBN: (纸本)0769519261

Content addressable memory is an expensive component in fixed architecture systems however it may prove to be a valuable tool in online architectures (that is, run-time reconfigurable systems with an online decision algorithm to determine the next reconfiguration). In this paper we define a related problem called an arbitrary mapping function and describe an online architecture. We look at four implementations of an arbitrary mapping function component and compare them in terms of space (number of CLB used), reconfiguration time, and component latency. All of the implementations offer low latency;which is the primary reason to use a content addressable memory or an arbitrary mapping function. Three of the implementations trade large size for very fast reconfiguration while the last implementation is extremely conservative in space but has a large reconfiguration time. © 2003 IEEE.

关键词： Mapping

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Reconfigurable mapping functions for online architectures

Reconfigurable mapping functions for online architectures

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： S. Harinath R. Sass Parallel Architecture Research Lab Holcombe Department of Electrical and Computer Engineering Clemson University Clemson SC USA

Content addressable memory is an expensive component in fixed architecture systems however it may prove to be a valuable tool in online architectures (that is, run-time reconfigurable systems with an online decision algorithm to determine the next reconfiguration). In this paper we define a related problem called an arbitrary mapping function and describe an online architecture. We look at four implementations of an arbitrary mapping function component and compare them in terms of space (number of CLB used), reconfiguration time, and component latency. All of the implementations offer low latency; which is the primary reason to use a content addressable memory or an arbitrary mapping function. Three of the implementations trade large size for very fast reconfiguration while the last implementation is extremely conservative in space but has a large reconfiguration time.

关键词： Associative memory computer architecture Delay Logic programming computer aided manufacturing CADCAM Logic arrays Reconfigurable logic Feedback loop parallel architectures

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