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PC platform power distribution system-past application, today's challenge and future direction

PC platform power distribution system-past application, toda...

引用

International Conference on Telecommunications Energy (INTELEC)

作者： J. Drobnik L. Huang P. Jain R. Steigerwald Platform Architecture Laboratory Intel Corporation Portland OR USA Department of Electrical & Computer Engineering Concordia University Montreal QUE Canada Corporate Research & Development General Electric Company Limited Schenectady NY USA

Segments of the PC industry have gone through dramatic changes. The future is even more challenging. Centralized DC power distribution has been extensively applied in most PC platforms today. This paper addresses limitations with conventional PC power distribution. Some processor roadmaps anticipate that PC platform power distribution will be analyzed and discussed in detail in the next five to ten years. This paper discusses future development direction and some novel design approaches.

关键词： Power distribution Voltage Power supplies Costs Frequency Regulators Capacitors USA Councils Electricity supply industry Microcomputers

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FACET: PC-parallel architecture for cost-efficient telemetry processing

FACET: PC-parallel architecture for cost-efficient telemetry...

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1998 IEEE Aerospace Conference, AERO 1998

作者： El-Ghazawi, Tarek Chalermwat, Prachya Piamsa-Nga, Punpiti Ozkaya, Armagan Speciale, Nick Wilson, Donald Computer Engineering and Computer Science Florida Institute of Technology MelbourneFL312901-6975 United States Parallel Architecture Laboratory Department of Electrical Engineering and Computer Science George Washington University WashingtonDC20052 United States NASA GSFC GreenbeltMD20771 United States

ISBN: (纸本)0780343115

NASA's Mission to Planet Earth (MTPE) is planning to launch the Earth Observing System (EOS) starting in 1998. The large number of planned remote sensing satellites will bring 500 Gigabytes of information per day. The EOS Data and Information System (EOSDIS) is responsible for ingesting and archiving this data. One important component of the EOSDIS system is the data operation, which involves extracting the packets and reconstructing and archiving the original remotely sensed data products. Due to transmission errors, the way data is sampled from the different sensors encoded, packets typically arrive out of order and perhaps with some of them missing or repeated. Many special hardware solutions have been proposed to solve this real-time problem. In this paper, we demonstrate a commercial off the shelf (COTS) solution. The hardware capitalizes on the progress made in the area of network of workstations (NOW), particularly PC-clusters. The software and algorithm exploit the data characteristics and parallelism in the telemetry stream to make use of load balancing and efficient parallel processing. It is shown that this solution can provide high-performance to cost and programmability. © 1998 IEEE.

关键词： parallel architectures

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Special ATPG to correlate test patterns for low-overhead mixed-mode BIST

Special ATPG to correlate test patterns for low-overhead mix...

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Asian Test Symposium (ATS)

作者： M. Karkala N.A. Touba H.-J. Wunderlich Computer Engineering Research Center Department of Electrical and Computer Engineering University of Technology Austin TX USA Computer Architecture Laboratory University of Stuttgart Stuttgart Germany

In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random patterns. While previous work in mixed-mode BIST has focused on developing hardware schemes for more efficiently encoding a given set of deterministic patterns (generated by a conventional ATPG procedure), the approach taken in this paper is to improve the encoding efficiency (and hence reduce hardware overhead) by specially selecting a set of deterministic test patterns for the r.p.r. faults that can be efficiently encoded. A special ATPG procedure is described for finding test patterns for the r.p.r. faults that are correlated (have the same logic value) in many bit positions. Such test patterns can be efficiently encoded with one of the many "bit-fixing" schemes that have been described in the literature. Results are shown for different bit-fixing schemes which indicate dramatic reductions in BIST overhead can be achieved by using the proposed ATPG procedure to select which test patterns to encode.

关键词： Automatic test pattern generation Built-in self-test Circuit testing Test pattern generators Circuit faults Read only memory Encoding Automatic testing Fault detection Character generation

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FACET: PC-parallel architecture for cost-efficient telemetry processing

FACET: PC-parallel architecture for cost-efficient telemetry...

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IEEE Conference on Aerospace

作者： T. El-Ghazawi P. Chalermwat P. Piamsa-nga A. Ozkaya N. Speciale D. Wilson Computer Engineering and Computer Science Florida Institute of Technology Melbourne FL USA Parallel Architecture Laboratory Department of Electrical Engineering and Computer Science George Washington University Washington D.C. DC USA NASA Goddard Space Flight Center Greenbelt MD USA

关键词： Telemetry Earth Observing System Hardware Planets Remote sensing Satellites Information systems Data mining Out of order Workstations

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Adaptive blocks: A high performance data structure 97

Adaptive blocks: A high performance data structure

引用

1997 ACM/IEEE Conference on Supercomputing, SC 1997

作者： Stout, Quentin F. De Zeeuw, Darren L. Gombosi, Tamas I. Groth, Clinton P. T. Marshall, Hal G. Powell, Kenneth G. Electrical Engineering and Computer Science Center for Parallel Computing University of Michigan Ann Arbor MI 48109-2122 United States Space Physics Research Laboratory Department of Atmospheric Oceanic and Space Sciences University of Michigan Ann Arbor MI 48109-2143 United States Laboratory for Scientific Computation Center for Parallel Computing University of Michigan Ann Arbor MI 48109-2094 United States Department of Aerospace Engineering University of Michigan Ann Arbor MI 48109-2118 United States

ISBN: (纸本)0897919858

We examine a data structure which uses flexible "adaptivity" to obtain high performance for both serial and parallel computers. The data structure is an adaptive grid which partitions a given region into regular cells. Its closest relatives are cell-based tree decompositions, but there are several important differences which lead to significant performance advantages. Using this block data structure to support adaptive mesh refinement (AMR), we were able to sustain 17 GFLOPS in ideal magnetohydrodynamic (MHD) simulations of the solar wind emanating from the base of the solar corona, using a 512 processor Cray T3D at NASA Goddard. © 1997 ACM.

关键词： Magnetohydrodynamics

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A technique to determine power-efficient, high-performance superscalar processors 28

A technique to determine power-efficient, high-performance s...

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28th Annual Hawaii International Conference on System Sciences, HICSS 1995

作者： Conte, T.M. Menezes, K.N.P. Sathaye, S.W. Computer Architecture Research Laboratory Department of Electrical and Computer Engineering University of South Carolina ColumbiaSC29208 United States

ISBN: (纸本)0818669306

Processor performance advances are increasingly inhibited by limitations in thermal power dissipation. Part of the problem is the lack of architectural power estimates before implementation. Although high-performance designs exist that dissipate low power, the method for finding these designs has been through trial-and-error. The paper presents systematic techniques to find low-power, high-performance superscalar processors tailored to specific user benchmarks. The model of power is novel because it separates power into architectural and technology components. The architectural component is found via trace-driven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is based on case studies of actual designs. It is used to solve an important problem: Increasing the duplication in superscalar execution units without excessive power consumption. Results are presented from runs using simulated annealing to maximize processor performance subject to power and area constraints. The major contributions of the paper are the separation of architectural and technology components of dynamic power, the use of trace-driven simulation for architectural power measurement, and the use of a near-optimal search to tailor a processor design to a benchmark. © 1995 IEEE.

关键词： Simulated annealing

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Data streaming: very low overhead communication for fine-grained multicomputing

Data streaming: very low overhead communication for fine-gra...

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： P.T. Gaughan Computer Architecture Research Laboratory Department of Electrical Engineering University of Alabama Tuscaloosa AL USA

Recent developments have greatly reduced network latencies in multiprocessor networks. Thus, software overhead is becoming the primary cost of multiprocessor communication. This paper proposes data streaming-a technique which places explicit send and receive instructions in the user code-as a means to cut software overhead to a minimum. Data streaming has the added benefit that it can tighten the coupling between processors by reducing the message size to that of a single data item. This paper presents experimental results that indicate data streaming can cut software overhead to less than one instruction per byte of data transmitted.

关键词： Costs Delay Switches Operating systems Yarn Traffic control Hardware computer architecture Laboratories Electronic mail

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A technique to determine power-efficient, high-performance superscalar processors

A technique to determine power-efficient, high-performance s...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： T.M. Conte K.N.P. Menezes S.W. Sathaye Computer Architecture Research Laboratory Department of Electrical and Computer Engineering University of South Carolina Columbia SC USA

Processor performance advances are increasingly inhibited by limitations in thermal power dissipation. Part of the problem is the lack of architectural power estimates before implementation. Although high-performance designs exist that dissipate low power, the method for finding these designs has been through trial-and-error. The paper presents systematic techniques to find low-power, high-performance superscalar processors tailored to specific user benchmarks. The model of power is novel because it separates power into architectural and technology components. The architectural component is found via trace-driven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is based on case studies of actual designs. It is used to solve an important problem: increasing the duplication in superscalar execution units without excessive power consumption. Results are presented from runs using simulated annealing to maximize processor performance subject to power and area constraints. The major contributions of the paper are the separation of architectural and technology components of dynamic power, the use of trace-driven simulation for architectural power measurement, and the use of a near-optimal search to tailor a processor design to a benchmark.< >

关键词： Power system modeling Delay estimation Power dissipation Delay effects Energy consumption Simulated annealing Paper technology Power measurement Process design

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Accuracy of filtered traces

Accuracy of filtered traces

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International Phoenix Conference on computers and Communications (IPCCC)

作者： S.K. Das E.E. Johnson Klipsch Dept. of Electr. & Comput. Eng. New Mexico State Univ. Las Cruces NM USA Parallel Architecture Research Laboratory Klipsch Department of Electrical and Computer Engineering New Mexico State University USA

Reducing the size of large address traces by "filtering" them through a small direct-mapped cache is a useful technique for making more efficient use of both secondary storage and processors used for trace-driven simulation. However, when filtered traces are used to drive cache simulators, the distortion introduced by such filtering can produce substantial errors in the miss ratios obtained, despite earlier reports to the contrary. We present the results of a systematic study of such errors, including a model for compensating for some errors.< >

关键词： computer errors Information filtering Information filters Computational modeling computer simulation Cache memory parallel architectures Laboratories Cache storage Drives

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Optimal space compaction of test responses

Optimal space compaction of test responses

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IEEE International Test Conference

作者： K. Chakrabarty B.T. Murray J.P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA General Motors Research and Development Center Warren MI USA

Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q/spl Lt/k, a process termed space compaction. The effectiveness of a compaction method can be measured by its compaction ratio c=k/q. However, a high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio c/sub max/. We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. For a given circuit tender test, a given fault model, and a given test set, we determine q/sub min/, which yields c/sub max/=k/q/sub min/. This provides a fundamental bound on the cost of signature based BIST. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS-85 benchmark circuits.

关键词： Compaction Circuit testing Circuit faults Built-in self-test Automatic testing computer architecture Laboratories research and development Q measurement Costs

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