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IEEE Instrumentation and Measurement Technology Conference

作者： I. Andreadis A. Amanatiadis Laboratory of Electronics Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece

The proposed scaling algorithm outperforms other standard and widely used scaling techniques. The algorithm uses a mask of maximum four pixels and calculates the final luminosity of each pixel combining two factors; the percentage of area that mask covers from each source pixel and the difference in luminosity between the source pixels. The interpolation is capable of scaling both grey-scale and color images of any resolution in any scaling factor. Its key characteristics and low complexity make the interpolation very fast and capable of real time implementation. The performance results in a variety of standard tests are presented and compared to other scaling algorithms

关键词： Digital images Pixel Filters Interpolation Testing Color Image resolution Laboratories Information systems Tellurium

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Home / Building Automation Environment Architecture Enabling Interoperability, Flexibility and Reusability

Home / Building Automation Environment Architecture Enabling...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： K. Charatsis A.P. Kalogeras M. Georgoudakis J. Gialelis G. Papadopoulos Industrial Systems Institute Patras Greece Applied Electronics Laboratory Department of Electrical and Computer Engineering University of Patras Patras Greece

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Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Dynamic coarse grain dataflow reconfiguration technique for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

关键词： Real time systems Switches Integrated circuit interconnections computer architecture Pipeline processing Reconfigurable architectures Design methodology Throughput Digital signal processing parallel processing

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Time-domain noise analysis of linear time-invariant and linear time-variant systems using MATLAB and HSPICE

Time-domain noise analysis of linear time-invariant and line...

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作者： Terry, Stephen C. Blalock, Benjamin J. Rochelle, James M. Nance Ericson, M. Caylor, Sam D. Department of Electrical and Computer Engineering University of Tennessee Knoxville TN 37996 United States Concorde Microsystems Inc. Knoxville TN 37932 United States Monolithic Systems Group Oak Ridge National Laboratory Oak Ridge TN 37831-6006 United States

A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear time-variant (LTV) systems. MATLAB is used to generate a set of representative noise signals, which are imported into HSPICE for simulation. Once the simulations are complete the results are read back into MATLAB and ensemble statistics are calculated. The MATLAB-generated noise signals have a user-defined white-noise floor and flicker-noise corner frequency and thus are suitable for modeling a wide variety of electronic components, including CMOS transistors and resistors. Simulation results of the time-dependent output noise of a gated integrator and the timing resolution of a gated integrator/comparator detector are presented to highlight both the utility and the versatility of the tool. © 2005 IEEE.

关键词： White noise

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Guest editorial wireless overlay networks based on mobile IPv6

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IEEE Journal on Selected Areas in Communications 2005年第11期23卷 2089-2090页

作者： Chao, Han-Chieh Huang, Nen-Fu Kuo, Sy-Yen Perkins, Charles E. Stuttgen, Heinrich Bux, W. National Ilan University Department of Electronic Engineering I-Lan 260 Taiwan National Tsing Hua University Department of Computer Science Hsin-Chu 300 Taiwan National Taiwan University Department of Electrical Engineering Taipei 106 Taiwan Nokia Research Center Communication Systems Laboratory Mountain View CA 94043 United States NEC Europe Ltd. Network Laboratories Heidelberg D 69115 Heidelberg Germany Department of Electronic Engineering Taiwan Library and Information Technology Office National Ilan University I-Lan Taiwan IPv6 Steering Committee Taiwan Taiwan IPv6 Forum Taiwan Department of Computer Science National Tsing Hua University Taiwan IPv6 Working Group NICI Ipv6 Steering Committee IPv6 Forum Taiwan Department of Electrical Engineering National Taiwan University Taiwan Computer Science and Engineering Department Chinese University of Hong Kong Hong Kong IEEE Computer Society Networking Technology Laboratory Nokia Research Center Mountain View CA United States IEEE Vehicular Technology Conference Networking Track NEC Europe Ltd. Germany NEC's Network Laboratories Heidelberg Germany Board of Governors IEEE Communications Society Japan Department of ComSoc's Switching Routing Technical Committee

No abstract available

关键词： Internet Wireless networks Mobile computing computer networks Land mobile radio cellular systems Access protocols GSM Pervasive computing Mobile communication computer architecture

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A dynamic compilation framework for controlling microprocessor energy and performance

A dynamic compilation framework for controlling microprocess...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Qiang Wu V.J. Reddi Youfeng Wu Jin Lee D. Connors D. Brooks M. Martonosi D.W. Clark Depts. of Computer Science Electrical Engineering Princeton University USA Department of Electrical and Computer Engineering University of Colorado Boulder USA Programming Systems Laboratory Intel Corporation USA Division of Engineering and Applied Science Harvard University USA

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control

关键词： Dynamic compiler Microprocessors Performance loss Voltage control Hardware Energy measurement Dynamic voltage scaling Frequency Energy management Microarchitecture

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Workflow - coordinated integration of enterprise/ industrial systems based on a semantic service - oriented architecture

Workflow - coordinated integration of enterprise/ industrial...

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International Conference on Emerging Technologies and Factory Automation (ETFA)

作者： C. Alexakos A.P. Kalogeras S. Likothanassis J. Gialelis S. Koubias Pattern Recognition Laboratory Department of Computer Engineering and Informatics University of Patras Rio Greece Industrial Systems Institute Science Park Platani Greece Pattern Recognition Laboratory Department of Computer Engineering and Informatics Engineering and Informatics University of Patras Rio Greece Research Academic Computer Technology Institute Patras Greece Applied Electronics Laboratory Department of Electrical and Computer Engineering University of Patras Rio Greece

Enterprise integration is significant for the enforcement of novel business models in an enterprise/industry. The great heterogeneity of systems/applications in the enterprise environment requires the introduction of interoperability aspects in order to resolve integration problems in a flexible and dynamic way. Our approach introduces an advanced enterprise semantic model representing both enterprise structure and available services, through the use of ontologies. The model is associated by a specific architecture that uses the above model in combination with state-of-the-art technologies such as Web services and workflows

关键词： Application software Ontologies Web services Semantic Web computer architecture Service oriented architecture Logic Internet Electronics industry Industrial electronics

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Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

Minimization of secondary effects in SOI: a 32-bit ANT logic...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Wasson Dipti Sanghvi A. Nunez VLSI Systems Design and CAD (VSDCAD) Laboratory Department of Electrical Engineering and Computer Science (EECS) Syracuse University Syracuse NY USA

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

关键词： Minimization Silicon on insulator technology Adders CMOS logic circuits Circuit synthesis CMOS technology Threshold voltage Noise reduction Circuit noise Logic design

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Pre-layout parasitic estimation in interconnects

Pre-layout parasitic estimation in interconnects

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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Advanced enterprise process modelling utilizing ontology semantics

Advanced enterprise process modelling utilizing ontology sem...

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International Conference on Emerging Technologies and Factory Automation (ETFA)

作者： J. Gialelis A.P. Kalogeras C. Alexakos M. Georgoudakis S. Koubias Applied Electronics Laboratory Electrical and Computer Engineering Department University of Patras Rio-Patras Greece Industrial Systems Institute Platani Greece

Ontologies present a state-of-the-art technology for the provision of machine-readable semantics. Its utilization for the annotation of end-to-end enterprise/industrial processes characterizing advanced collaborative business models, largely contributes to enterprise interoperability, flexibility and component reusability. Our work in this paper emphasizes on the use of ontologies in combination with workflows for business process modeling and presents an associated methodology and architecture

关键词： Ontologies Manufacturing industries Collaboration Collaborative work Production Manufacturing processes Enterprise resource planning Service oriented architecture Communication industry Consumer electronics

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